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11. 发明授权

US06717877B2 Semiconductor integration circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06717877B2
公开(公告)日：2004-04-06
申请号：US10038663
申请日：2002-01-08
申请人： Takeshi Suzuki , Shigeru Nakahara , Keiichi Higeta , Takeshi Kusunoki
发明人： Takeshi Suzuki , Shigeru Nakahara , Keiichi Higeta , Takeshi Kusunoki
IPC分类号： G11C700
CPC分类号： G11C7/227 , G11C7/22 , G11C11/419 , G11C2207/2254 , G11C2207/2281
摘要： A semiconductor integrated circuit device includes a first variable delay circuit which delays a timing signal for activating a sense amplifier which is supplied with a signal read out from a memory array and amplifies the signal so that a timing difference between a dummy signal read out from a dummy memory cell and the timing signal of the sense amplifier is detected by a detection circuit to be made small in accordance with an output of the detection circuit, and a second variable delay circuit which adjusts a relative timing difference between the dummy signal and the timing signal of the sense amplifier.
摘要翻译：半导体集成电路装置包括：第一可变延迟电路，其延迟用于激活读出放大器的定时信号，读出放大器被提供有从存储器阵列读出的信号，并放大该信号，使得从一个根据检测电路的输出，由检测电路检测出虚拟存储单元和读出放大器的定时信号，使其变小，以及第二可变延迟电路，其调整虚拟信号与定时之间的相对定时差感测放大器的信号。

12. 发明授权

US07009246B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07009246B2
公开(公告)日：2006-03-07
申请号：US10772391
申请日：2004-02-06
申请人： Takahiro Kawata , Shigeru Nakahara , Keiichi Higeta
发明人： Takahiro Kawata , Shigeru Nakahara , Keiichi Higeta
IPC分类号： H01L29/72
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0928 , H01L27/1104
摘要： To reduce the width of isolation between the first and second p channel MIS•FETs driven by different voltages, a first p channel MIS•FET driven by a first supply voltage and a second p channel MIS•FET driven by a second supply voltage higher than the first supply voltage are arranged in the same n well of the same semiconductor substrate, and the second supply voltage is supplied as a common well bias voltage to the n well.
摘要翻译：为了减小由不同电压驱动的第一和第二p沟道MIS.FET之间的隔离宽度，由第一电源电压驱动的第一p沟道MIS.FET和由第二电源电压高于第一电源电压被布置在相同半导体衬底的相同n阱中，并且第二电源电压作为公共阱偏置电压被提供给n阱。

13. 发明授权

US06791895B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06791895B2
公开(公告)日：2004-09-14
申请号：US10671475
申请日：2003-09-29
申请人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
发明人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
IPC分类号： G11C700
CPC分类号： G11C11/417 , G11C11/412
摘要： A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.
摘要翻译：一种具有包括CMOS触发器电路型存储单元的存储器阵列的半导体存储器件，其能够提高噪声容限，使得读取速度快并降低功耗。在半导体存储器件中，将存储单元的工作电压设定得高于外围电路的工作电压。构成存储单元的MOS晶体管的阈值电压被设定为高于构成外围电路的MOS晶体管的阈值电压。构成存储单元的MOS晶体管的栅极绝缘膜形成为当被转换为相同材料的绝缘膜时，构成构成外围电路的MOS晶体管的栅极绝缘膜更厚。此外，字线选择电平和位线预充电电平被设置为与外围电路的工作电压的电平相同。

14. 发明授权

US07012848B2 Semiconductor integrated circuit device 失效
公开(公告)号：US07012848B2
公开(公告)日：2006-03-14
申请号：US10917320
申请日：2004-08-13
申请人： Satoshi Iwahashi , Shigeru Nakahara , Takeshi Suzuki , Keiichi Higeta
发明人： Satoshi Iwahashi , Shigeru Nakahara , Takeshi Suzuki , Keiichi Higeta
IPC分类号： G11C7/00
CPC分类号： G11C7/1069 , G11C7/1051 , G11C8/16 , G11C11/4125
摘要： The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.

15. 发明申请

US20050146947A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050146947A1
公开(公告)日：2005-07-07
申请号：US11011427
申请日：2004-12-15
申请人： Keiichi Higeta , Satoshi Iwahashi , Yoichiro Aihara , Shigeru Nakahara
发明人： Keiichi Higeta , Satoshi Iwahashi , Yoichiro Aihara , Shigeru Nakahara
IPC分类号： G11C15/04 , G11C16/04 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , G11C15/04 , G11C15/043 , H01L27/1104
摘要： Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.
摘要翻译：数据线（D 0，D 1）由第一存储部分（MA）和第二存储部分（MB）共享，此外，第一晶体管（MC 0）耦合到第一比较数据部分（CD 0）和耦合到第一存储部分的存储节点的第二晶体管（MCA）串联连接以形成第一比较电路（11）和耦合到第二比较数据线（CD 1）的第三晶体管（MC 1）和耦合到第二存储部分的存储节点的第四晶体管（MCB）串联连接以形成第二比较电路（12）。因此，可以提高扩散层和布线层的布局的对称性，并且实现存储单元相对于穿过其中心的中心线线对称的布局的容易性。因此，可以容易地优化制造工艺条件，并且可以降低制造工艺的变化，从而可以实现存储单元的微细加工。

16. 发明授权

US06876573B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06876573B2
公开(公告)日：2005-04-05
申请号：US10917321
申请日：2004-08-13
申请人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
发明人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
IPC分类号： G11C8/02 , G11C11/41 , G11C11/412 , G11C11/413 , G11C11/417 , H01L21/8244 , H01L27/10 , H01L27/11 , G11C11/00
CPC分类号： G11C11/417 , G11C11/412
摘要： A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.
摘要翻译：一种具有包括CMOS触发器电路型存储单元的存储器阵列的半导体存储器件，其能够提高噪声容限，使得读取速度快并降低功耗。在半导体存储器件中，将存储单元的工作电压设定得高于外围电路的工作电压。构成存储单元的MOS晶体管的阈值电压被设定为高于构成外围电路的MOS晶体管的阈值电压。构成存储单元的MOS晶体管的栅极绝缘膜形成为当被转换为相同材料的绝缘膜时，构成构成外围电路的MOS晶体管的栅极绝缘膜更厚。此外，字线选择电平和位线预充电电平被设置为与外围电路的工作电压的电平相同。

17. 发明授权

US06512709B1 Semiconductor integrated circuit 失效
公开(公告)号：US06512709B1
公开(公告)日：2003-01-28
申请号：US10173429
申请日：2002-06-18
申请人： Shigeru Nakahara , Hideki Hayashi , Takeshi Suzuki , Keiichi Higeta
发明人： Shigeru Nakahara , Hideki Hayashi , Takeshi Suzuki , Keiichi Higeta
IPC分类号： G11C700
CPC分类号： G11C29/848 , G11C29/028 , G11C29/44 , G11C29/50012 , G11C29/787 , G11C29/789 , G11C29/802 , G11C2029/1208 , G11C2029/4402
摘要： A semiconductor integrated circuit having therein a plurality of memories, realizing an improved yield by efficiently repairing a defective bit in a memory. This semiconductor integrated circuit has: a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code or not and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the setting information from the setting circuit, converting the setting information to parallel data, and transferring the parallel data to the plurality of circuit blocks. Each of the plurality of circuit blocks captures and holds the setting information transferred when the identification code coincidence detecting circuit determines that the input identification code and the self identification code coincide with each other.

18. 发明授权

US06445627B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06445627B1
公开(公告)日：2002-09-03
申请号：US09886026
申请日：2001-06-22
申请人： Shigeru Nakahara , Hideki Hayashi , Takeshi Suzuki , Keiichi Higeta
发明人： Shigeru Nakahara , Hideki Hayashi , Takeshi Suzuki , Keiichi Higeta
IPC分类号： G11C700
CPC分类号： G11C29/848 , G11C29/028 , G11C29/44 , G11C29/50012 , G11C29/787 , G11C29/789 , G11C29/802 , G11C2029/1208 , G11C2029/4402
摘要： A semiconductor integrated circuit can efficiently repair a defective bit in a memory and comprises a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the set information from the setting circuit, converting the set information to parallel data, and transferring the parallel data to the plurality of circuit blocks. Each of the plurality of circuit blocks captures and holds the set information transferred when the identification code coincidence detecting circuit determines that the input identification code and the self identification code coincide.
摘要翻译：半导体集成电路可以有效地修复存储器中的有缺陷的位，并且包括多个电路块（RAM宏单元），每个电路块具有识别码重合检测电路，用于确定输入的识别码是否与自身识别码和接收数据一致锁存并根据锁存数据执行操作; 设置电路，其能够设置与识别码相对应的识别码和信息，并且串行地输出设定信息; 以及控制电路，能够从设定电路依次读取设定信息，将设定信息转换成并行数据，并将并行数据传送给多个电路块。当识别码一致检测电路确定输入的识别码和自身识别码一致时，多个电路块中的每一个捕获并保持传送的设置信息。

19. 发明授权

US5701425A Data processor with functional register and data processing method 失效
标题翻译：具有功能寄存器和数据处理方式的数据处理器
公开(公告)号：US5701425A
公开(公告)日：1997-12-23
申请号：US704362
申请日：1996-08-28
申请人： Shigeru Nakahara
发明人： Shigeru Nakahara
IPC分类号： G06F9/315 , G06F9/30 , G06F9/318 , G06F9/34 , G06F9/355 , G06F1/04
CPC分类号： G06F9/30181
摘要： A data processor has a functional register which subjects data written thereto and reads therefrom, to predefined operations. The functional register is specified in an instruction so that the data can be processed in various manners by combining the processing of an instruction specified by its operation code and a specific function allocated to the functional register.
摘要翻译：数据处理器具有功能寄存器，其对写入到其中的数据进行读取，并将其读取到预定义的操作。在指令中指定功能寄存器，使得可以通过组合由其操作码指定的指令与分配给功能寄存器的特定功能的处理，以各种方式处理数据。

20. 发明申请

US20090243658A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：US20090243658A1
公开(公告)日：2009-10-01
申请号：US12350681
申请日：2009-01-08
申请人： Akinori YOKOI , Shigeru Nakahara
发明人： Akinori YOKOI , Shigeru Nakahara
IPC分类号： H03K19/0944 , H01L29/68 , H01L21/336 , H01L29/78
CPC分类号： H01L27/0629 , H01L27/0805
摘要： A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance. At this point in time, a resistance value as desired is attained through combination of decoupling capacitors having threshold voltages Vth differing from each other.
摘要翻译：在高技术的情况下需要使用由具有增强的静电击穿电阻的交叉耦合去耦电容器表示的去耦电容器，由于IR降低而导致电源线上AC噪声降低的电路。还提供了用于抑制由于共振而导致的电源线上的交流噪声的电路。构成具有增强的静电击穿电阻的交叉耦合去耦电容器的MOS晶体管具有较低的阈值电压Vth，从而减小每个MOS晶体管的源极和漏极之间的电阻，导致IR降低。此外，阻尼电阻对于抑制电源线上的AC噪声是有效的，并且每个MOS晶体管的源极到漏极电阻被用作阻尼电阻。在这个时间点，通过组合具有彼此不同的阈值电压Vth的去耦电容来获得希望的电阻值。

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