专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20110309516A1 SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20110309516A1
公开(公告)日：2011-12-22
申请号：US12819796
申请日：2010-06-21
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
IPC分类号： H01L23/538 , H01L21/768 , H01L21/60
CPC分类号： H01L23/48 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/06513 , H01L2225/06531 , H01L2225/06541 , H01L2924/00014 , H01L2924/1815 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance. The third signal coupling pads are disposed on the second non-top metal layer and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap variation between the first signal coupling pads of the first chip and the third signal coupling pads of the second chip is under stringent control of the second distance and the fourth distance. Therefore, the mass-production yield of the semiconductor package is increased.
摘要翻译：半导体封装及其制造方法技术领域本发明涉及半导体封装及其制造方法。半导体封装包括第一芯片和第二芯片。第一芯片包括第一有源表面，至少一个第一非顶部金属层和多个第一信号耦合焊盘。第一非顶部金属层设置成与第一有源表面相邻并间隔开第二距离。第一信号耦合焊盘设置在第一非顶部金属层上。第二芯片电连接到第一芯片。第二芯片包括第二有源表面，至少一个第二非顶部金属层和多个第三信号耦合焊盘。第二活性表面面向第一芯片的第一有效表面。第二非顶部金属层被布置成与第二有源表面相邻并且与第二有源表面间隔开第四距离。第三信号耦合焊盘设置在第二非顶部金属层上，并电容耦合到第一芯片的第一信号耦合焊盘，从而提供第一芯片与第二芯片之间的接近通信。由此，第一芯片的第一信号耦合焊盘与第二芯片的第三信号耦合焊盘之间的间隙变化受到第二距离和第四距离的严格控制。因此，半导体封装的批量生产量增加。

12. 发明申请

US20110298139A1 Semiconductor Package 审中-公开
标题翻译：半导体封装
公开(公告)号：US20110298139A1
公开(公告)日：2011-12-08
申请号：US12794390
申请日：2010-06-04
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
IPC分类号： H01L23/538 , H01L23/52
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/3171 , H01L23/48 , H01L23/49816 , H01L23/5383 , H01L24/05 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L2224/0401 , H01L2224/16225 , H01L2224/16227 , H01L2224/48091 , H01L2224/4824 , H01L2224/731 , H01L2224/85 , H01L2225/06527 , H01L2225/06562 , H01L2924/00014 , H01L2924/01033 , H01L2924/01076 , H01L2924/014 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/30105 , H01L2924/30107 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and a second chip. The substrate has a first surface, a second surface and at least one through hole. The first chip is disposed adjacent to the first surface of the substrate. The first chip includes a first active surface and a plurality of first signal pads. Part of the first active surface is exposed to the through hole. The position of the first signal pads corresponds to the through hole. The second chip is disposed adjacent to the second surface. The second chip includes a second active surface and a plurality of second signal pads. Part of the second active surface is exposed to the through hole. The position of the second signal pads corresponds to the through hole, and the second signal pads are capacitively coupled to the first signal pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the strength of the first chip and the second chip is increased after being mounted to the substrate, so the yield of the semiconductor package is increased.
摘要翻译：本发明涉及半导体封装。半导体封装包括衬底，第一芯片和第二芯片。衬底具有第一表面，第二表面和至少一个通孔。第一芯片设置在基板的第一表面附近。第一芯片包括第一有源表面和多个第一信号焊盘。第一活性表面的一部分暴露于通孔。第一信号垫的位置对应于通孔。第二芯片设置成与第二表面相邻。第二芯片包括第二有源表面和多个第二信号焊盘。第二活性表面的一部分暴露于通孔。第二信号焊盘的位置对应于通孔，并且第二信号焊盘电容耦合到第一芯片的第一信号焊盘，以便提供第一芯片和第二芯片之间的邻近通信。由此，第一芯片和第二芯片的强度在安装到基板之后增加，因此增加了半导体封装的成品率。

13. 发明申请

US20110227212A1 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件封装及其制造方法
公开(公告)号：US20110227212A1
公开(公告)日：2011-09-22
申请号：US12729034
申请日：2010-03-22
申请人： Ming-Hsiang CHENG , Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Ming-Hsiang CHENG , Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： H01L23/00 , H01L21/50
CPC分类号： H01L25/0652 , H01L23/053 , H01L25/50 , H01L2224/16225 , H01L2924/15311 , H01L2924/15331 , H01L2924/19105
摘要： A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a first substrate, a second substrate, two active chips, a bridge chip and a connection structure. The first substrate has a first surface facing a second surface of the second substrate. The active chips are disposed on and electrically connected to the first surface, and spaced apart from each other by an interval, wherein the active chips respectively have a first active surface. The bridge chip is mechanically and electrically connected to the second surface, and has a second active surface partially overlapped with the first active surfaces of the active chips, such that the bridge chip is used for providing a proximity communication between the active chips. The connection structure is disposed between the first surface and the second surface for combining the first substrate and the second substrate.
摘要翻译：公开了一种半导体器件封装及其制造方法。半导体器件封装包括第一衬底，第二衬底，两个有源芯片，桥芯片和连接结构。第一基板具有面向第二基板的第二表面的第一表面。有源芯片设置在第一表面上并电连接到第一表面，并且间隔彼此间隔开，其中有源芯片分别具有第一有源表面。桥芯片机械地和电连接到第二表面，并且具有与有源芯片的第一有源表面部分地重叠的第二有源表面，使得桥接芯片用于提供有源芯片之间的邻近通信。连接结构设置在第一表面和第二表面之间，用于组合第一基板和第二基板。

14. 发明申请

US20090051048A1 Package structure and manufacturing method thereof 审中-公开
标题翻译：包装结构及其制造方法
公开(公告)号：US20090051048A1
公开(公告)日：2009-02-26
申请号：US12222610
申请日：2008-08-13
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L24/32 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/91 , H01L2224/05571 , H01L2224/05573 , H01L2224/13099 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2224/81136 , H01L2224/81192 , H01L2224/81801 , H01L2224/83051 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/181 , H01L2224/78 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A package structure and a manufacturing method thereof are provided. The package structure includes a carrier, a chip-bonding structure and a chip. The chip-bonding structure is formed on a first surface of the carrier. The chip-bonding structure includes a cavity, a dam, several via holes and several solder bumps. The solder bumps are received in the via holes and are correspond to the first connecting pads located on the carrier. The chip is embedded in the cavity of the chip-bonding structure. An active surface of the chip is tightly pasted on the first surface of the chip-bonding structure, and the first solder pads form electrical contact with the corresponding solder bumps. The chip of the package structure is precisely disposed on the carrier, not only simplifying the manufacturing process but also forming stable electrical connection between the chip and the carrier of the package structure.
摘要翻译：提供一种封装结构及其制造方法。封装结构包括载体，芯片结合结构和芯片。芯片接合结构形成在载体的第一表面上。芯片结合结构包括空腔，坝，几个通孔和几个焊料凸块。焊料凸块被容纳在通孔中并且对应于位于载体上的第一连接焊盘。芯片嵌入在芯片结合结构的空腔中。芯片的有源表面被牢固地粘贴在芯片接合结构的第一表面上，并且第一焊盘与相应的焊料凸块形成电接触。封装结构的芯片精确地布置在载体上，不仅简化了制造工艺，而且还在封装结构的芯片和载体之间形成稳定的电连接。

15. 发明授权

US07980757B2 Bonding strength measuring device 有权
标题翻译：接合强度测量装置
公开(公告)号：US07980757B2
公开(公告)日：2011-07-19
申请号：US12350643
申请日：2009-01-08
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： G01K1/00 , G01N25/00
CPC分类号： G01N19/04
摘要： A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.
摘要翻译：提供了用于测量基板和设置在基板上的模塑料之间的接合强度的接合强度测量装置。测量装置包括加热平台，加热滑板和固定支架。加热平台具有第一加热区域和第一可更换夹具。基板设置在第一加热区域上，并且第一可更换夹具用于固定基板，并具有露出模塑料的开口。加热滑板具有第二加热区域和第二可更换夹具。第二加热区域用于加热模塑料，第二可更换夹具具有容纳模塑料的空腔。固定支架用于将加热滑板固定在加热平台上。

16. 发明申请

US20090175312A1 BONDING STRENGTH MEASURING DEVICE 有权
标题翻译：粘结强度测量装置
公开(公告)号：US20090175312A1
公开(公告)日：2009-07-09
申请号：US12350643
申请日：2009-01-08
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： G01N3/00
CPC分类号： G01N19/04
摘要： A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.
摘要翻译：提供了用于测量基板和设置在基板上的模塑料之间的接合强度的接合强度测量装置。测量装置包括加热平台，加热滑板和固定支架。加热平台具有第一加热区域和第一可更换夹具。基板设置在第一加热区域上，并且第一可更换夹具用于固定基板，并具有露出模塑料的开口。加热滑板具有第二加热区域和第二可更换夹具。第二加热区域用于加热模塑料，第二可更换夹具具有用于容纳模塑料的空腔。固定支架用于将加热滑板固定在加热平台上。

17. 发明授权

US08115285B2 Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof 有权
标题翻译：具有保护层以提高表面安装及其制造方法的高级四边形扁平无铅芯片封装
公开(公告)号：US08115285B2
公开(公告)日：2012-02-14
申请号：US12192805
申请日：2008-08-15
申请人： Chien-Wen Chen , Yi-Shao Lai , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Pao-Huei Chang Chien , Ping-Cheng Hu , Hsu-Yang Lee
发明人： Chien-Wen Chen , Yi-Shao Lai , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Pao-Huei Chang Chien , Ping-Cheng Hu , Hsu-Yang Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.
摘要翻译：描述半导体封装和相关方法。在一个实施例中，封装包括管芯焊盘，多个引线，芯片，封装体和保护层。管芯焊盘包括上倾斜部分，下倾斜部分和限定具有空腔底部的空腔的周边边缘区域。每个引线包括上倾斜部分和下倾斜部分。芯片设置在腔体底部并耦合到引线。封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。保护层基本上覆盖至少一个引线的下倾斜部分和下表面。

18. 发明授权

US07964949B2 Tenon-and-mortise packaging structure 有权
标题翻译：榫眼包装结构
公开(公告)号：US07964949B2
公开(公告)日：2011-06-21
申请号：US12216637
申请日：2008-07-09
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang , Tsan-Hsien Chen
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang , Tsan-Hsien Chen
IPC分类号： H01L23/02
CPC分类号： H01L23/3107 , H01L25/03 , H01L25/16 , H01L2225/0652 , H01L2225/06555 , H01L2225/06586 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.
摘要翻译：提供包括载体和芯片的榫眼包装结构。载体具有与顶表面相对的顶表面和下表面。顶表面形成至少一个榫头突起，并且下表面形成对应于形状，尺寸和位置的榫头突起的榫槽，使得两个载体可以通过将榫头投影连接到彼此并且彼此连接相应的榫槽。榫头和榫槽分别具有导电部分。当榫头突起和榫槽彼此接合时，导电部分彼此电连接。至少一个芯片嵌入在载体中。芯片分别具有有源表面和背面，并与载体的顶表面和下表面电连接。

19. 发明申请

US20120119342A1 ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：先进的四边平面非引线封装结构及其制造方法
公开(公告)号：US20120119342A1
公开(公告)日：2012-05-17
申请号：US12944695
申请日：2010-11-11
申请人： Pao-Huei Chang Chien , Ping-Cheng Hu , Po-Shing Chiang , Wei-Lun Cheng , Hsueh-Te Wang , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Ping-Feng Yang
发明人： Pao-Huei Chang Chien , Ping-Cheng Hu , Po-Shing Chiang , Wei-Lun Cheng , Hsueh-Te Wang , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Ping-Feng Yang
IPC分类号： H01L23/495 , H01L21/58 , H01L21/56
CPC分类号： H01L21/4832 , H01L21/561 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/4911 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound.
摘要翻译：先进的四边形扁平无铅封装结构包括载体，芯片，多根导线和模塑料。载体包括管芯焊盘和多个引线。引线的内引线被设计成具有弯曲的侧壁，用于增强内引线和周围模塑料之间的粘附。

20. 发明申请

US20090096077A1 Tenon-and-mortise packaging structure 有权
标题翻译：榫眼包装结构
公开(公告)号：US20090096077A1
公开(公告)日：2009-04-16
申请号：US12216637
申请日：2008-07-09
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang , Tsan-Hsien Chen
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang , Tsan-Hsien Chen
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L23/3107 , H01L25/03 , H01L25/16 , H01L2225/0652 , H01L2225/06555 , H01L2225/06586 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.
摘要翻译：提供包括载体和芯片的榫眼包装结构。载体具有与顶表面相对的顶表面和下表面。顶表面形成至少一个榫头突起，并且下表面形成对应于形状，尺寸和位置的榫头突起的榫槽，使得两个载体可以通过将榫头投影连接到彼此并且彼此连接相应的榫槽。榫头和榫槽分别具有导电部分。当榫头突起和榫槽彼此接合时，导电部分彼此电连接。至少一个芯片嵌入在载体中。芯片分别具有有源表面和背面，并与载体的顶表面和下表面电连接。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式