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11. 发明授权

US06717620B1 Method and apparatus for decompressing compressed data 失效
标题翻译：用于解压缩压缩数据的方法和装置
公开(公告)号：US06717620B1
公开(公告)日：2004-04-06
申请号：US09096550
申请日：1998-06-12
申请人： Paul Chow , Allen J. Porter , David A. Strasser , Antonio Asaro , Indra Laksono , Biljana D. Simsic
发明人： Paul Chow , Allen J. Porter , David A. Strasser , Antonio Asaro , Indra Laksono , Biljana D. Simsic
IPC分类号： H04N1104
CPC分类号： H04N19/433 , H04N19/44
摘要： A method and apparatus for decompressing compressed data, which includes video data that has been compressed in accordance with the MPEG 2 standard, wherein the processing begins by retrieving components from a non-local memory at a rate that is independent of the rate in which the components were written into the non-local memory. The components include motion vectors and run/level data. As the components are retrieved from memory, the run/level data is used to produce representations of the uncompressed data. As the representations of the uncompressed data are generated, they are processed based on the motion vector data to recapture the uncompressed data. The uncompressed data is then stored in a frame buffer for subsequent display.
摘要翻译：一种用于解压缩压缩数据的方法和装置，其包括已经根据MPEG2标准被压缩的视频数据，其中该处理开始于以非速率独立于非本地存储器组件被写入非本地内存。这些组件包括运动矢量和运行/电平数据。当从存储器检索组件时，运行/级别数据用于产生未压缩数据的表示。当生成未压缩数据的表示时，将基于运动矢量数据对它们进行处理，以重新获取未压缩的数据。然后将未压缩的数据存储在帧缓冲器中用于随后的显示。

12. 发明授权

US06643756B1 System and method for accessing video data using a translation client 有权
标题翻译：使用翻译客户端访问视频数据的系统和方法
公开(公告)号：US06643756B1
公开(公告)日：2003-11-04
申请号：US09438308
申请日：1999-11-11
申请人： Milivoje Aleksic , Nader Akhlaghi-Tavasoli , Jason Chan , Carl Mizuyabu , Antonio Asaro
发明人： Milivoje Aleksic , Nader Akhlaghi-Tavasoli , Jason Chan , Carl Mizuyabu , Antonio Asaro
IPC分类号： G06F1200
CPC分类号： G06F3/14 , G06F12/1027 , G06F12/1081
摘要： A request for video or graphics data is made to a memory controller. When the memory controller determines a translation of the data must first be made, a request is made to a translator. The translator either translates the address or requests translation information from the memory controller. The memory controller accesses memory based upon the translator request. If the request is for translation data the results are tagged for the translator. If the translator request is for the translated address, the results are tagged for the original request.
摘要翻译：对存储器控制器进行视频或图形数据的请求。当存储器控制器确定首先需要进行数据的转换时，向翻译器发出请求。翻译器翻译来自存储器控制器的地址或请求翻译信息。存储器控制器根据翻译器请求访问存储器。如果请求用于翻译数据，则结果将被标记为翻译器。如果翻译请求是用于翻译的地址，结果将被标记为原始请求。

13. 发明授权

US06339427B1 Graphics display list handler and method 有权
标题翻译：图形显示列表处理程序和方法
公开(公告)号：US06339427B1
公开(公告)日：2002-01-15
申请号：US09211637
申请日：1998-12-15
申请人： Indra Laksono , Antonio Asaro
发明人： Indra Laksono , Antonio Asaro
IPC分类号： G06T1500
CPC分类号： G06T15/005
摘要： A graphics display command list handler and method requests allocation of memory, such as system memory, in the form of a circular FIFO which stores the display command list as a memory display list (MDL), such as a host memory display list. A processor, such as a graphics processor, communicates a host memory display list read pointer to the host processor to facilitate display list signaling by the graphics processor. The host processor (or other processor) maintains a write pointer which points to a last host memory entry in the display list. The read pointer is maintained by the graphics processor and written back to the host processor.
摘要翻译：图形显示命令列表处理程序和方法请求以循环FIFO的形式分配诸如系统存储器的存储显示命令列表作为诸如主机存储器显示列表的存储器显示列表（MDL）的存储器。诸如图形处理器的处理器将主机存储器显示列表读取指针传送到主机处理器以便于图形处理器的显示列表信令。主机处理器（或其他处理器）维护写入指针，该指针指向显示列表中的最后一个主机存储器条目。读指针由图形处理器维护并写回到主处理器。

14. 发明授权

US6100906A Method and apparatus for improved double buffering 失效
标题翻译：改进双缓冲的方法和装置
公开(公告)号：US6100906A
公开(公告)日：2000-08-08
申请号：US64569
申请日：1998-04-22
申请人： Antonio Asaro , Indra Laksono , James Doyle , Gordon F. Grigor
发明人： Antonio Asaro , Indra Laksono , James Doyle , Gordon F. Grigor
IPC分类号： G09G5/36 , G09G5/39 , G09G5/393 , G09G5/399 , G06F13/00
CPC分类号： G09G5/399 , G09G5/363
摘要： A method and apparatus for improved double buffering within a computing system begins when a series of data blocks are received from a central processing unit at a rate independent of a processing rate of a recipient engine. For example, a video graphics circuit receives a series of data blocks representing video frames from the central processing unit at a rate independent of the refresh rate of the display. As the data blocks are received, the video graphics circuit queues commands of the data blocks. Typically, the commands include processing commands and a processing rate synchronize command. To process the data blocks, the co-processor pulls commands from the queued list and processes them to produce recipient data. As the co-processor is producing the recipient data, it is utilizing a first buffer. The co-processor continues to process the commands and storing the results into the first buffer until the processing rate synchronize command is detected. At this point, the co-processor pauses processing of the commands. At the beginning of the next cycle of the processing rate, the recipient data is provided from the first buffer to the recipient engine and the co-processor resumes processing of commands, which relate to another data block. As the co-processor is processing the commands of the second data block, it is utilizing a second buffer to store the processed data, i.e., the second recipient data.
摘要翻译：一种用于在计算系统内改进双缓冲的方法和装置开始于以与接收机发动机的处理速率无关的速率从中央处理单元接收一系列数据块时开始。例如，视频图形电路以与显示器的刷新率无关的速率从中央处理单元接收表示视频帧的一系列数据块。当数据块被接收时，视频图形电路对数据块的命令进行排队。通常，命令包括处理命令和处理速率同步命令。为了处理数据块，协处理器从排队列表中提取命令并处理它们以产生接收方数据。当协处理器产生接收者数据时，它正在利用第一缓冲器。协处理器继续处理命令并将结果存储到第一缓冲器中，直到检测到处理速率同步命令。此时，协处理器暂停处理命令。在处理速率的下一周期的开始，从第一缓冲器向接收者引擎提供接收者数据，并且协处理器恢复与另一个数据块有关的命令的处理。当协处理器正在处理第二数据块的命令时，它利用第二缓冲器来存储经处理的数据，即第二接收者数据。

15. 发明授权

US06469703B1 System of accessing data in a graphics system and method thereof 有权
标题翻译：在图形系统中访问数据的系统及其方法
公开(公告)号：US06469703B1
公开(公告)日：2002-10-22
申请号：US09347202
申请日：1999-07-02
申请人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
IPC分类号： G06F15167
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the 10 controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，10个控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。

16. 发明授权

US06195105B1 Method and apparatus for improved concurrent video graphic processing 失效
标题翻译：用于改进并发视频图形处理的方法和装置
公开(公告)号：US06195105B1
公开(公告)日：2001-02-27
申请号：US09088190
申请日：1998-06-01
申请人： Steven C. Dilliplane , Indra Laksono , Antonio Asaro
发明人： Steven C. Dilliplane , Indra Laksono , Antonio Asaro
IPC分类号： G06T120
CPC分类号： G06F9/3877 , G06F9/30025
摘要： A method and apparatus for improved concurrency within a video graphics process by generating culling information from geometry information. The geometry information corresponds to an image to be rendered, and the culling information indicates the triangles of the objects of the image that are in a front-facing or back-facing position. Having generated the culling information, set-up information is generated therefrom. The set-up information provides rendering data for the triangles of the object of the image being rendered. Next, pixel data is generated for a triangle based on the set-up information. To improve the concurrency, the queuing and the retrieval of the culling information and the set-up information from non-local memory are controlled such that the generating of the culling information, the set-up information, and the pixel data is done with improved concurrency.
摘要翻译：一种用于通过从几何信息生成剔除信息来改善视频图形过程中的并发性的方法和装置。几何信息对应于要呈现的图像，并且剔除信息指示图像的处于前向或后向位置的图像的三角形。生成了拣选信息后，从其生成设置信息。设置信息提供正在呈现的图像的对象的三角形的渲染数据。接下来，基于设置信息为三角形生成像素数据。为了提高并发性，对来自非本地存储器的排队信息和设置信息的排队和检索进行控制，使得剔除信息，建立信息和像素数据的生成被改进并发性

17. 发明授权

US08645639B2 Hierarchical memory arbitration technique for disparate sources 有权
标题翻译：不同来源的分层内存仲裁技术
公开(公告)号：US08645639B2
公开(公告)日：2014-02-04
申请号：US13600614
申请日：2012-08-31
申请人： Guhan Krishnan , Antonio Asaro , Don Cherepacha , Thomas R. Kunjan , Joerg Winkler , Ralf Flemming , Maurice B. Steinman , Jonathan Owen , John Kalamatianos
发明人： Guhan Krishnan , Antonio Asaro , Don Cherepacha , Thomas R. Kunjan , Joerg Winkler , Ralf Flemming , Maurice B. Steinman , Jonathan Owen , John Kalamatianos
IPC分类号： G06F13/18
CPC分类号： G06F13/161
摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.
摘要翻译：分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。合并的非相干存储器请求流基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

18. 发明授权

US08266389B2 Hierarchical memory arbitration technique for disparate sources 有权
标题翻译：不同来源的分层内存仲裁技术
公开(公告)号：US08266389B2
公开(公告)日：2012-09-11
申请号：US12431874
申请日：2009-04-29
申请人： Guhan Krishnan , Antonio Asaro , Don Cherepacha , Thomas R. Kunjan , Joerg Winkler , Ralf Flemming , Maurice B. Steinman , Jonathan Owen , John Kalamatianos
发明人： Guhan Krishnan , Antonio Asaro , Don Cherepacha , Thomas R. Kunjan , Joerg Winkler , Ralf Flemming , Maurice B. Steinman , Jonathan Owen , John Kalamatianos
IPC分类号： G06F13/18
CPC分类号： G06F13/161
摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.
摘要翻译：分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。合并的非相干存储器请求流至少部分地基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

19. 发明申请

US20120331226A1 HIERARCHICAL MEMORY ARBITRATION TECHNIQUE FOR DISPARATE SOURCES 有权
标题翻译：不同来源的分层记忆仲裁技术
公开(公告)号：US20120331226A1
公开(公告)日：2012-12-27
申请号：US13600614
申请日：2012-08-31
申请人： Guhan Krishnan , Antonio Asaro , Don Cherepacha , Thomas R. Kunjan , Joerg Winkler , Ralf Flemming , Maurice B. Steinman , Jonathan Owen , John Kalamatianos
发明人： Guhan Krishnan , Antonio Asaro , Don Cherepacha , Thomas R. Kunjan , Joerg Winkler , Ralf Flemming , Maurice B. Steinman , Jonathan Owen , John Kalamatianos
IPC分类号： G06F12/08
CPC分类号： G06F13/161
摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.
摘要翻译：分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。合并的非相干存储器请求流基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

20. 发明授权

US06448974B1 Method and apparatus for chroma key data modifying insertion without video image fragmentation 有权
标题翻译：用于色度密钥数据修改插入而无视频图像碎片的方法和装置
公开(公告)号：US06448974B1
公开(公告)日：2002-09-10
申请号：US09259372
申请日：1999-02-26
申请人： Antonio Asaro , Edward Callway
发明人： Antonio Asaro , Edward Callway
IPC分类号： G06T1140
CPC分类号： G06T11/001
摘要： A method and apparatus for enhanced image display that substantially eliminates video image fragments include processing that begins by monitoring color data of an image to be displayed. The processing then continues by determining whether at least a portion of the image includes color data that matches a chroma key color. When at least a portion of the image includes color data that matches the chroma key color, the processing continues by adjusting the color of at least a portion of the image to produce adjusted color data such that the adjusted color data does not match the chroma key color.
摘要翻译：用于基本上消除视频图像片段的用于增强图像显示的方法和装置包括通过监视要显示的图像的颜色数据开始的处理。然后通过确定图像的至少一部分是否包括与色度键颜色匹配的颜色数据来继续处理。当图像的至少一部分包括与色度键颜色匹配的颜色数据时，通过调整图像的至少一部分的颜色来继续处理以产生调整的颜色数据，使得调整的颜色数据与色度键不匹配颜色。

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