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    • 20. 发明授权
    • Semiconductor device output buffer circuit for LSI
    • LSI半导体器件输出缓冲电路
    • US6072354A
    • 2000-06-06
    • US939334
    • 1997-09-29
    • Toshikazu TachibanaTakeshi SakaiYoshinobu Nakagome
    • Toshikazu TachibanaTakeshi SakaiYoshinobu Nakagome
    • H03K19/017H03K17/16
    • H03K19/01714Y10T307/438
    • In a semiconductor device having a plurality of output circuits such as a semiconductor memory device, a drive signal having a boosted voltage level which is produced from a boosting circuit is applied to a gate of a low-level outputting MOS transistor in the output circuit. As a result, even when a potential at the ground wiring line is floated, a substantial decrease of a potential difference between the ground wiring line and the gate of the low-level outputting MOS transistor can be prevented. Also, a signal having a sufficiently high level can be supplied to a gate of a low-level outputting output MOS transistor. As a consequence, delays in the switching operation of the output MOS transistor can be suppressed, and the output circuit can be operated at high speed.
    • 在具有诸如半导体存储器件的多个输出电路的半导体器件中,将由升压电路产生的升压电压电平的驱动信号施加到输出电路中的低电平输出MOS晶体管的栅极。 结果,即使在接地布线的电位浮起时,也可以防止接地布线和低电平输出MOS晶体管的栅极之间的电位差的显着降低。 此外,具有足够高电平的信号可以被提供给低电平输出输出MOS晶体管的栅极。 结果,可以抑制输出MOS晶体管的开关操作的延迟,并且输出电路可以高速运行。