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11. 发明申请

US20050187997A1 Flexible accumulator in digital signal processing circuitry 失效
标题翻译：灵活的累加器在数字信号处理电路中
公开(公告)号：US20050187997A1
公开(公告)日：2005-08-25
申请号：US10783789
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Hwang , Kumara Tharmalingam
IPC分类号： G06F7/38 , G06F7/544
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit. The least significant bits (LSBs) can be tied to ground and sent along the feedback path. To initialize the accumulator value, the MSBs of the initialization value can be input to the MAC block and sent directly to the add-subtract-accumulate unit. The LSBs can be sent to another multiplier that performs a multiply-by-one operation before being sent to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。最低有效位（LSB）可以连接到地并沿反馈路径发送。要初始化累加器值，初始化值的MSB可以输入到MAC块，并直接发送到加减法累加单元。可以将LSB发送到另一个乘法器，该乘法器在发送到加减法累加单元之前执行乘法运算。

12. 发明授权

US09170775B2 Flexible accumulator in digital signal processing circuitry 有权
标题翻译：灵活的累加器在数字信号处理电路中
公开(公告)号：US09170775B2
公开(公告)日：2015-10-27
申请号：US12683686
申请日：2010-01-07
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
IPC分类号： G06F7/38 , G06F7/544
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

13. 发明授权

US08228102B1 Phase-locked loop architecture and clock distribution system 有权
标题翻译：锁相环架构和时钟分配系统
公开(公告)号：US08228102B1
公开(公告)日：2012-07-24
申请号：US12717062
申请日：2010-03-03
申请人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
发明人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
IPC分类号： H03L7/06
CPC分类号： H03L7/23 , G06F1/10 , H03L7/0807 , H03L7/183 , H03L7/197 , H03L7/1974 , H04L7/0331
摘要： One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，该集成电路包括集成电路的第一侧上的第一条锁相环（PLL）电路，以及集成电路的第二侧的第二条PLL电路，该第二条与第一条侧。可以通过对集成电路进行编程来配置第一和第二条带中的PLL电路。另一实施例涉及包括多个锁相环（PLL）电路和与多个PLL电路相邻的多个物理介质连接（PMA）三元组模块的集成电路。每个PMA三元组模块包括第一，第二和第三通道。第一和第三通道被布置为用作接收通道，并且第二通道被布置为可配置为接收通道或时钟倍增单元。还公开了其它实施例和特征。

14. 发明授权

US07930336B2 Large multiplier for programmable logic device 有权
标题翻译：可编程逻辑器件的大倍数
公开(公告)号：US07930336B2
公开(公告)日：2011-04-19
申请号：US11566982
申请日：2006-12-05
申请人： Martin Langhammer , Kumara Tharmalingam
发明人： Martin Langhammer , Kumara Tharmalingam
IPC分类号： G06F7/52
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
摘要翻译：可编程逻辑器件中的多个专用处理块，包括用于将这些乘法器的结果相加的乘法器和电路的多个专用处理块可以被配置为较大的乘法器，通过将添加到专用处理块的可选择电路来移位乘法器结果。在一个实施例中，这允许在专门的处理块中进行除最终添加之外的所有添加，最后的加法发生在可编程逻辑中。在另一个实施例中，附加的压缩和加法电路甚至允许在专门的处理块中发生最后的添加。

15. 发明申请

US20100169404A1 FLEXIBLE ACCUMULATOR IN DIGITAL SIGNAL PROCESSING CIRCUITRY 审中-公开
标题翻译：数字信号处理电路中的灵活累加器
公开(公告)号：US20100169404A1
公开(公告)日：2010-07-01
申请号：US12683686
申请日：2010-01-07
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
IPC分类号： G06F7/44 , G06F7/42
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

16. 发明申请

US20080133627A1 LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：用于可编程逻辑器件的大型多路复用器
公开(公告)号：US20080133627A1
公开(公告)日：2008-06-05
申请号：US11566982
申请日：2006-12-05
申请人： Martin Langhammer , Kumara Tharmalingam
发明人： Martin Langhammer , Kumara Tharmalingam
IPC分类号： G06F7/57 , G06F17/00
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
摘要翻译：可编程逻辑器件中的多个专用处理块，包括用于将这些乘法器的结果相加的乘法器和电路的多个专用处理块可以被配置为较大的乘法器，通过将添加到专用处理块的可选择电路来移位乘法器结果。在一个实施例中，这允许在专门的处理块中进行除最终添加之外的所有添加，最后的加法发生在可编程逻辑中。在另一个实施例中，附加的压缩和加法电路甚至允许在专门的处理块中发生最后的添加。

17. 发明授权

US08788562B2 Large multiplier for programmable logic device 有权
标题翻译：可编程逻辑器件的大倍数
公开(公告)号：US08788562B2
公开(公告)日：2014-07-22
申请号：US13042700
申请日：2011-03-08
申请人： Martin Langhammer , Kumara Tharmalingam
发明人： Martin Langhammer , Kumara Tharmalingam
IPC分类号： G06F7/52
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
摘要翻译：可编程逻辑器件中的多个专用处理块，包括用于将这些乘法器的结果相加的乘法器和电路的多个专用处理块可以被配置为较大的乘法器，通过将添加到专用处理块的可选择电路来移位乘法器结果。在一个实施例中，这允许在专门的处理块中进行除最终添加之外的所有添加，最后的加法发生在可编程逻辑中。在另一个实施例中，附加的压缩和加法电路甚至允许在专门的处理块中发生最后的添加。

18. 发明授权

US08612795B1 Segmented clock network for transceiver array 有权
标题翻译：收发器阵列的分段时钟网络
公开(公告)号：US08612795B1
公开(公告)日：2013-12-17
申请号：US12847268
申请日：2010-07-30
申请人： Weiqi Ding , Kumara Tharmalingam
发明人： Weiqi Ding , Kumara Tharmalingam
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G11C7/222
摘要： One embodiment relates to a clocking network interconnecting an array of transceivers. The clocking network includes first and second series of multiplexers, each multiplexer in the first and second series being adjacent to a transceiver. The first series of multiplexers selectively transmits clock signals in a first direction of the array, and the second series of multiplexers selectively transmits clock signals in a second direction of the array. Another embodiment relates to an integrated circuit with a programmable interface. The integrated circuit includes an array of physical media attachment circuits, phase-locked loop circuits, and a clock distribution network. The clock distribution network is arranged to be programmed into multiple segments. Each segment distributes a clock signal to a bounded range of the physical media attachment circuits in the array. Another embodiment relates to a method of distributing clock signals in an integrated circuit. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及互连收发器阵列的时钟网络。时钟网络包括第一和第二系列多路复用器，第一和第二系列中的每个多路复用器与收发器相邻。第一系列多路复用器选择性地在阵列的第一方向上传输时钟信号，并且第二系列多路复用器选择性地在阵列的第二方向上传输时钟信号。另一实施例涉及具有可编程接口的集成电路。集成电路包括物理介质连接电路，锁相环电路和时钟分配网络的阵列。时钟分配网络被布置成被编程成多个段。每个段将时钟信号分配到阵列中物理介质连接电路的有界范围。另一实施例涉及在集成电路中分配时钟信号的方法。还公开了其它实施例和特征。

19. 发明授权

US08171443B1 Circuit design tools that support devices with real-time phase-locked loop reconfiguration capabilities 有权
标题翻译：电路设计工具支持具有实时锁相环重配置能力的设备
公开(公告)号：US08171443B1
公开(公告)日：2012-05-01
申请号：US13110793
申请日：2011-05-18
申请人： Ian Eu Meng Chan , Kumara Tharmalingam
发明人： Ian Eu Meng Chan , Kumara Tharmalingam
IPC分类号： G06F17/50 , G06F15/177 , G06F9/00
CPC分类号： G06F17/5054 , G06F17/505 , H03L7/08
摘要： Computer-aided-design tools are provided that support real-time phase-locked loop reconfiguration with a single design compilation. Each design compilation may involve operations such as logic synthesis and place and route operations. A circuit designer who is designing an integrated circuit may supply circuit design data. The circuit design data may include design data for multiple configurations of a phase-locked loop. By using a phase-locked loop scan chain initialization file generator engine located in a CAD tool design input wizard, the computer-aided-design tools may produce multiple phase-locked loop initialization files without performing a design compilation. The CAD tools may process one or more initialization files and the circuit design data to produce output data. The output data may include configuration data to implement the circuit design. The output data may also include warning messages that indicate when phase-locked loop settings in an initialization file do not match settings in the circuit design.
摘要翻译：提供了计算机辅助设计工具，通过单一设计编译支持实时锁相环重新配置。每个设计编译可能涉及诸如逻辑综合和放置和路由操作之类的操作。设计集成电路的电路设计者可以提供电路设计数据。电路设计数据可以包括用于锁相环的多个配置的设计数据。通过使用位于CAD工具设计输入向导中的锁相环扫描链初始化文件生成器引擎，计算机辅助设计工具可以产生多个锁相环初始化文件，而不执行设计编译。 CAD工具可以处理一个或多个初始化文件和电路设计数据以产生输出数据。输出数据可以包括用于实现电路设计的配置数据。输出数据还可以包括警告消息，其指示初始化文件中的锁相环设置与电路设计中的设置不匹配。

20. 发明授权

US07660841B2 Flexible accumulator in digital signal processing circuitry 失效
标题翻译：灵活的累加器在数字信号处理电路中
公开(公告)号：US07660841B2
公开(公告)日：2010-02-09
申请号：US10783789
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

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