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11. 发明申请

US20140014904A1 Replacement Contacts for All-Around Contacts 有权
标题翻译：全方位联系人的替换联系人
公开(公告)号：US20140014904A1
公开(公告)日：2014-01-16
申请号：US13558532
申请日：2012-07-26
申请人： Guy M. Cohen , Michael A. Guillorn
发明人： Guy M. Cohen , Michael A. Guillorn
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/413 , H01L29/42364 , H01L29/66439
摘要： In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device.
摘要翻译：一方面，提供一种FET器件。 FET器件包括衬底; 衬底上的半导体材料; 所述衬底上的至少一个栅极围绕用作所述器件的沟道区的所述半导体材料的一部分，其中从所述栅极延伸的所述半导体材料的部分用作所述器件的源极和漏极区域，并且其中所述源极和器件的漏极区域从衬底移位; 覆盖栅极和半导体材料的器件上的平坦化电介质; 以及延伸穿过平坦化电介质并且围绕器件的源极和漏极区域的触点。

12. 发明授权

US08586455B1 Preventing shorting of adjacent devices 失效
标题翻译：防止相邻设备短路
公开(公告)号：US08586455B1
公开(公告)日：2013-11-19
申请号：US13471487
申请日：2012-05-15
申请人： Josephine Chang , Michael A. Guillorn , Balasubramanian Pranatharthiharan , Jeffrey William Sleight
发明人： Josephine Chang , Michael A. Guillorn , Balasubramanian Pranatharthiharan , Jeffrey William Sleight
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/76202 , H01L21/823431 , H01L21/845 , H01L27/1104 , H01L27/1108
摘要： Embodiments of the present invention provide a method of preventing electrical shorting of adjacent semiconductor devices. The method includes forming a plurality of fins of a plurality of field-effect-transistors on a substrate; forming at least one barrier structure between a first and a second fin of the plurality of fins; and growing an epitaxial film from the plurality of fins, the epitaxial film extending horizontally from sidewalls of at least the first and second fins and reaching the barrier structure situating between the first and second fins.
摘要翻译：本发明的实施例提供一种防止相邻半导体器件的电短路的方法。该方法包括在衬底上形成多个场效应晶体管的多个散热片; 在所述多个翅片的第一和第二翅片之间形成至少一个阻挡结构; 以及从所述多个翅片生长外延膜，所述外延膜从至少所述第一和第二鳍片的侧壁水平延伸并到达位于所述第一和第二鳍片之间的所述阻挡结构。

13. 发明授权

US08492748B2 Collapsable gate for deposited nanostructures 失效
标题翻译：用于沉积的纳米结构的可折叠门
公开(公告)号：US08492748B2
公开(公告)日：2013-07-23
申请号：US13169542
申请日：2011-06-27
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Philip S. Waggoner
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Philip S. Waggoner
IPC分类号： H01L29/06 , H01L31/00 , H01L29/15 , H01L51/40
CPC分类号： H01L29/66045 , H01L51/055
摘要： A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.
摘要翻译：一次性材料层首先沉积在石墨烯层或碳纳米管（CNT）上。一次性材料层包括比石墨烯或CNT更不惰性的材料，使得可以以目标电介质厚度沉积连续的电介质材料层而没有针孔。通过图案化连续的介电材料层和沉积在其上的栅极导体层来形成栅极叠层。一次性材料层在形成栅极叠层期间屏蔽并保护石墨烯层或CNT。然后通过选择性蚀刻去除一次性材料层，释放独立的栅极结构。独立栅极结构在选择性蚀刻结束时在石墨烯层或CNT上折叠，使得连续介电材料层的底表面接触石墨烯层或CNT的上表面。

14. 发明授权

US08492208B1 Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process 有权
标题翻译：用替代栅极工艺制造的纳米线FET中的压电（PFET）和拉伸（NFET）沟道应变
公开(公告)号：US08492208B1
公开(公告)日：2013-07-23
申请号：US13344352
申请日：2012-01-05
申请人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
发明人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
IPC分类号： H01L21/00 , H01L29/76
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/66439
摘要： A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
摘要翻译：提供一种制造FET器件的方法，其包括以下步骤。纳米线/焊盘形成在BOX层上的SOI层中，其中纳米线悬挂在BOX上。沉积围绕纳米线的HSQ层。围绕纳米线的HSQ层的一部分交联，其中交联导致HSQ层的一部分收缩，从而诱导纳米线中的应变。形成一个或多个保持在纳米线中诱发的应变的栅极。还提供了一种FET器件，其中每个纳米线具有变形的第一区域，使得第一区域中的晶格常数小于纳米线的松弛晶格常数和第二区域，其变形使得第二区域中的晶格常数大于纳米线的松弛晶格常数。

15. 发明申请

US20130092992A1 REPLACEMENT GATE MULTIGATE TRANSISTOR FOR EMBEDDED DRAM 有权
标题翻译：嵌入式DRAM的更换栅极多晶硅晶体管
公开(公告)号：US20130092992A1
公开(公告)日：2013-04-18
申请号：US13274758
申请日：2011-10-17
申请人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
发明人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
IPC分类号： H01L27/108 , H01L21/02 , B82Y99/00
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译：存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。

16. 发明授权

US08216902B2 Nanomesh SRAM cell 有权
标题翻译： Nanomesh SRAM单元
公开(公告)号：US08216902B2
公开(公告)日：2012-07-10
申请号：US12536741
申请日：2009-08-06
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L21/8234
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L27/0688 , H01L27/11 , H01L27/1104 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.
摘要翻译：提供基于纳米线的设备。在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。

17. 发明授权

US08084308B2 Single gate inverter nanowire mesh 有权
标题翻译：单门逆变器纳米线网
公开(公告)号：US08084308B2
公开(公告)日：2011-12-27
申请号：US12470128
申请日：2009-05-21
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L21/00 , H01L21/84 , H01L27/148 , H01L27/105
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译：提供基于纳米线的设备。一方面，提供了场效应晶体管（FET）逆变器。 FET反相器包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个更多的器件层掺杂有n型掺杂剂，并且器件层中的一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。还提供了用于制造FET逆变器的技术。

18. 发明授权

US08003220B2 Nanotransfer and nanoreplication using deterministically grown sacrificial nanotemplates 有权
标题翻译：使用确定性生长的牺牲纳米模板进行纳米转移和纳米应用
公开(公告)号：US08003220B2
公开(公告)日：2011-08-23
申请号：US11985395
申请日：2007-11-13
申请人： Anatoli V. Melechko , Timothy E. McKnight , Michael A. Guillorn , Bojan Ilic , Vladimir I. Merkulov , Mitchel J. Doktycz , Douglas H. Lowndes , Michael L. Simpson
发明人： Anatoli V. Melechko , Timothy E. McKnight , Michael A. Guillorn , Bojan Ilic , Vladimir I. Merkulov , Mitchel J. Doktycz , Douglas H. Lowndes , Michael L. Simpson
IPC分类号： B32B9/00
CPC分类号： B01D67/0062 , B01D67/0069 , B01D67/0072 , B01D71/02 , B01D71/027 , B01D2323/24 , B01D2325/08 , B01J23/755 , B01J35/0013 , B01J35/006 , B01J37/0238 , B01J37/342 , B01L3/5027 , B01L2300/0663 , B01L2300/0896 , B81B2201/058 , B81B2203/0361 , B81C1/00119 , B82Y30/00 , Y10S977/70 , Y10S977/781 , Y10S977/784 , Y10T428/13 , Y10T428/1303 , Y10T428/1352 , Y10T428/1359 , Y10T428/139 , Y10T428/24174 , Y10T428/24273 , Y10T428/24322 , Y10T428/2902 , Y10T428/2991 , Y10T428/31504 , Y10T428/31678
摘要： Methods, manufactures, machines and compositions are described for nanotransfer and nanoreplication using deterministically grown sacrificial nanotemplates. An apparatus, includes a substrate and a nanoreplicant structure coupled to a surface of the substrate.
摘要翻译：使用确定性生长的牺牲纳米模板描述了用于纳米转移和纳米应用的方法，制造商，机器和组合物。一种装置，包括与衬底的表面耦合的衬底和纳米复合结构。

19. 发明授权

US07947976B2 Controlled alignment of catalytically grown nanostructures in a large-scale synthesis process 有权
标题翻译：在大规模合成过程中催化生长的纳米结构的对照排列
公开(公告)号：US07947976B2
公开(公告)日：2011-05-24
申请号：US12220888
申请日：2008-07-28
申请人： Vladimir I. Merkulov , Anatoli V. Melechko , Michael A. Guillorn , Douglas H. Lowndes , Michael L. Simpson
发明人： Vladimir I. Merkulov , Anatoli V. Melechko , Michael A. Guillorn , Douglas H. Lowndes , Michael L. Simpson
IPC分类号： H01L21/00
CPC分类号： G01N33/5438 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B2202/08 , D01F9/127 , Y10S977/843 , Y10S977/891 , Y10S977/943 , Y10T428/24628
摘要： Systems and methods are described for controlled alignment of catalytically grown nanostructures in a large-scale synthesis process. A method includes: generating an electric field proximate an edge of a protruding section of an electrode, the electric field defining a vector; and forming an elongated nanostructure located at a position on a surface of a substrate, the position on the surface of the substrate proximate the edge of the protruding section of the electrode, at least one tangent to the elongated nanostructure i) substantially parallel to the vector defined by the electric field and ii) substantially non-parallel to a normal defined by the surface of the substrate.
摘要翻译：描述了用于在大规模合成过程中催化生长的纳米结构的受控比对的系统和方法。一种方法包括：在电极的突出部分的边缘附近产生电场，所述电场限定矢量; 以及形成位于基底表面上的位置处的细长纳米结构，所述基底表面上靠近所述电极的突出部分的边缘的位置，至少一个细长纳米结构的切线i）基本上平行于所述载体由电场限定，ii）基本上不平行于由衬底的表面限定的法线。

20. 发明授权

US07893492B2 Nanowire mesh device and method of fabricating same 有权
标题翻译：纳米线网装置及其制造方法
公开(公告)号：US07893492B2
公开(公告)日：2011-02-22
申请号：US12371943
申请日：2009-02-17
申请人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/02
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.
摘要翻译：提供一种半导体结构，其包括位于衬底表面上的多个垂直堆叠且垂直间隔开的半导体纳米线（例如，半导体纳米线网）。每个垂直堆叠和垂直间隔开的半导体纳米线的一个端段连接到源极区域，并且每个垂直堆叠和垂直间隔开的半导体纳米线的另一个端部段连接到漏极区域。包括栅极电介质和栅极导体的栅极区域邻接多个垂直堆叠和垂直间隔的半导体纳米线，并且源极区域和漏极区域与栅极区域自对准。

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