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11. 发明授权

US07998846B2 3-D integrated circuit system and method 有权
标题翻译： 3-D集成电路系统及方法
公开(公告)号：US07998846B2
公开(公告)日：2011-08-16
申请号：US12209478
申请日：2008-09-12
申请人： Eunha Kim , Jeremy Wahl , Shenqing Fang , YouSeok Suh , Kuo-Tung Chang , Yi Ma , Rinji Sugino , Jean Yang
发明人： Eunha Kim , Jeremy Wahl , Shenqing Fang , YouSeok Suh , Kuo-Tung Chang , Yi Ma , Rinji Sugino , Jean Yang
IPC分类号： H01L21/263
CPC分类号： H01L21/02675 , H01L21/02592 , H01L21/02691
摘要： A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.
摘要翻译：提出了半导体制造系统和方法。三维多层集成电路制造方法可以包括通过利用受控激光层形成退火工艺形成第一器件层并在第一器件层顶部形成第二器件层，并以最小的有害热传递到第一层。可以利用受控激光结晶过程，并且受控激光器可以包括产生非晶层; 限定非晶层中的结晶区域，其中结晶区域被限定为促进单晶生长（即防止多晶生长）; 以及将激光施加到结晶区域，其中以防止不希望的热传递到另一层的方式施加激光。

12. 发明授权

US07907448B2 Scaled down select gates of NAND flash memory cell strings and method of forming same 有权
标题翻译：缩放NAND闪存单元串的选择门及其形成方法
公开(公告)号：US07907448B2
公开(公告)日：2011-03-15
申请号：US12246981
申请日：2008-10-07
申请人： YouSeok Suh , Shenqing Fang , Kuo-Tung Chang
发明人： YouSeok Suh , Shenqing Fang , Kuo-Tung Chang
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0483
摘要： A NAND flash memory cell string having scaled down select gates. The NAND flash memory cell string includes a first select gate that has a width of 140 nm or less and a plurality of wordlines that are coupled to the first select gate. Gates associated with the plurality of wordlines are formed of p+ polysilicon. A second select gate that has a width of 140 nm or less is coupled to the plurality of wordlines.
摘要翻译：具有按比例缩小的选择门的NAND快闪存储器单元串。 NAND闪存单元串包括具有140nm或更小的宽度的第一选择栅极和耦合到第一选择栅极的多个字线。与多个字线相关联的门由p +多晶硅形成。具有140nm或更小的宽度的第二选择栅极耦合到多个字线。

13. 发明授权

US07906395B2 Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀
公开(公告)号：US07906395B2
公开(公告)日：2011-03-15
申请号：US12891481
申请日：2010-09-27
申请人： Shenqing Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
发明人： Shenqing Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。然后在核心单元之间部分地蚀刻捕获层。进行捕获层上的氧化物的偏移。并形成顶部氧化物。顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

14. 发明授权

US07943980B2 Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications 有权
标题翻译：通过使用非保形膜的自对准图案化方法，并回扫闪存和其他半导体应用
公开(公告)号：US07943980B2
公开(公告)日：2011-05-17
申请号：US12891532
申请日：2010-09-27
申请人： Shenqing Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
发明人： Shenqing Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。然后在核心单元之间部分蚀刻捕获层。进行捕获层上的氧化物的偏移。并形成顶部氧化物。顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

15. 发明申请

US20080150005A1 MEMORY SYSTEM WITH DEPLETION GATE 审中-公开
标题翻译：带有隔离门的记忆系统
公开(公告)号：US20080150005A1
公开(公告)日：2008-06-26
申请号：US11694089
申请日：2007-03-30
申请人： Meng Ding , YouSeok Suh , Wei Zheng , Kuo-Tung Chang
发明人： Meng Ding , YouSeok Suh , Wei Zheng , Kuo-Tung Chang
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A memory system includes a substrate, forming a first insulator layer over the substrate, forming a charge-storage layer over the first insulator layer, forming a second insulator layer over the charge-storage layer, and forming a depletion gate having a depletion phenomenon over the second insulator layer.
摘要翻译：存储器系统包括：衬底，在衬底上形成第一绝缘体层，在第一绝缘体层之上形成电荷存储层，在电荷存储层上形成第二绝缘体层，并形成具有耗尽现象的耗尽栅极第二绝缘体层。

16. 发明申请

US20080171416A1 Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀
公开(公告)号：US20080171416A1
公开(公告)日：2008-07-17
申请号：US11653649
申请日：2007-01-12
申请人： Shenging Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
发明人： Shenging Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。然后在核心单元之间部分蚀刻捕获层。进行捕获层上的氧化物的偏移。并形成顶部氧化物。顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

17. 发明授权

US07803680B2 Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀
公开(公告)号：US07803680B2
公开(公告)日：2010-09-28
申请号：US11653649
申请日：2007-01-12
申请人： Shenging Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
发明人： Shenging Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。然后在核心单元之间部分蚀刻捕获层。进行捕获层上的氧化物的偏移。并形成顶部氧化物。顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

18. 发明申请

US20080096357A1 METHOD FOR MANUFACTURING A MEMORY DEVICE 审中-公开
标题翻译：用于制造存储器件的方法
公开(公告)号：US20080096357A1
公开(公告)日：2008-04-24
申请号：US11551535
申请日：2006-10-20
申请人： Youseok Suh , Hidehiko Shiraiwa , Allison Holbrook , Angela Hui , Kuo-Tung Chang
发明人： Youseok Suh , Hidehiko Shiraiwa , Allison Holbrook , Angela Hui , Kuo-Tung Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for manufacturing a memory device that includes using a gap-filling material that inhibits charge coupling between memory devices. A semiconductor material is provided that has an active region and an isolation region. A charge trapping structure is formed over the active region and a layer of semiconductor material is formed over the charge trapping structure and the isolation region. A masking structure having sidewalls is formed on the layer of semiconductor material. Spacers are formed adjacent the sidewalls and the layer of semiconductor material is etched to form one or more conductive strips having opposing sides. The one or more conductive strips are formed over the active region. A dielectric material is formed adjacent to the opposing sides of each conductive strip. The dielectric material serves as a gap-filling material. A layer of semiconductor material is formed over the one or more conductive strips.
摘要翻译：一种用于制造存储器件的方法，其包括使用禁止存储器件之间的电荷耦合的间隙填充材料。提供了具有有源区和隔离区的半导体材料。在有源区上形成电荷俘获结构，在电荷俘获结构和隔离区上形成一层半导体材料。在半导体材料层上形成具有侧壁的掩模结构。间隔件邻近侧壁形成，并且半导体材料层被蚀刻以形成具有相对侧面的一个或多个导电条。一个或多个导电条形成在有源区上。在每个导电带的相对侧附近形成电介质材料。介电材料用作间隙填充材料。在一个或多个导电条上形成半导体材料层。

19. 发明授权

US06927129B1 Narrow wide spacer 有权
标题翻译：狭窄的间距
公开(公告)号：US06927129B1
公开(公告)日：2005-08-09
申请号：US10821312
申请日：2004-04-08
申请人： Yu Sun , Kuo-Tung Chang , Angela T. Hui , Shenqing Fang
发明人： Yu Sun , Kuo-Tung Chang , Angela T. Hui , Shenqing Fang
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/105
CPC分类号： H01L29/6656 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： A method for fabricating a semiconductor device. Specifically, A method of manufacturing a semiconductor device comprising: depositing a first oxide layer over a periphery transistor comprising a gate stack, a drain side sidewall and a source side sidewall and over a core transistor comprising a gate stack, a source side sidewall and a drain side sidewall; etching the first oxide layer wherein a portion of the first oxide layer remains on the source side sidewall and on the drain side sidewall of the periphery transistor and on the source side sidewall and on the drain side sidewall of the core transistor; etching the first oxide layer from the source side sidewall of the core transistor; depositing a second oxide layer over the periphery transistor and the core transistor; and etching the second oxide layer wherein a portion of the second oxide layer remains on the first oxide layer formed on the source side sidewall and on the drain side sidewall of the periphery transistor and wherein the second oxide layer remains on the source side sidewall and on the drain side sidewall of the core transistor.
摘要翻译：一种半导体器件的制造方法。具体地说，一种制造半导体器件的方法，包括：在包括栅极堆叠，漏极侧壁和源极侧壁的外围晶体管上沉积第一氧化物层，以及包括栅极堆叠，源极侧壁和排水侧壁蚀刻第一氧化物层，其中第一氧化物层的一部分保留在外围晶体管的源极侧壁和漏极侧壁上，并且在芯晶体管的源极侧壁和漏极侧侧壁上残留; 从芯晶体管的源极侧壁蚀刻第一氧化物层; 在外围晶体管和芯晶体管上沉积第二氧化物层; 以及蚀刻所述第二氧化物层，其中所述第二氧化物层的一部分保留在形成在所述外围晶体管的源极侧壁和漏极侧壁上的第一氧化物层上，并且其中所述第二氧化物层保留在所述源侧侧壁上，芯晶体管的漏极侧壁。

20. 发明授权

US07029975B1 Method and apparatus for eliminating word line bending by source side implantation 有权
标题翻译：通过源侧植入消除字线弯曲的方法和装置
公开(公告)号：US07029975B1
公开(公告)日：2006-04-18
申请号：US10839561
申请日：2004-05-04
申请人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani
发明人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/513
摘要： A method and apparatus for coupling to a source line is disclosed. A semiconductor structure having an array of memory cells arranged in rows and columns is described. The array of memory cells includes a source region that is implanted with n-type dopants isolated between an adjoining pair of the non-intersecting STI regions and isolated from a drain region during the implantation. A source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells and the source contact is coupled to the source region for providing electrical coupling with a plurality of source lines. The isolating of the implanted source region from the drain region during the implanting enables coupling of the source contact to the source lines while maintaining the n-type dopants between the STI regions and avoiding lateral diffusion to a bit-line.
摘要翻译：公开了一种用于耦合到源极线的方法和装置。描述了具有排列成行和列的存储单元阵列的半导体结构。存储单元阵列包括源区域，其注入在相邻的一对不相交的STI区域之间隔离并在植入期间与漏区隔离的n型掺杂剂。源极触点沿着一排漏极触点排列，其被连接到一行存储器单元的漏极区域，并且源极触点耦合到源极区域以提供与多个源极线的电耦合。在植入期间将注入的源极区域与漏极区域隔离使得能够将源极接触耦合到源极线，同时保持STI区域之间的n型掺杂剂并且避免横向扩散到位线。

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