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11. 发明申请

US20100157854A1 SYSTEMS AND METHODS FOR SENDING DATA PACKETS BETWEEN MULTIPLE FPGA DEVICES 有权
标题翻译：用于发送多个FPGA器件之间的数据包的系统和方法
公开(公告)号：US20100157854A1
公开(公告)日：2010-06-24
申请号：US12340094
申请日：2008-12-19
申请人： Joshua D. Anderson , Scott M. Burkart , Matthew P. DeLaquil , Deepak Prasanna
发明人： Joshua D. Anderson , Scott M. Burkart , Matthew P. DeLaquil , Deepak Prasanna
IPC分类号： H04L12/56 , H04L29/02 , H04L5/14
CPC分类号： H04L45/00 , H04L49/10 , H04L49/25
摘要： Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Dynamically-sized data packets, sized in accordance with the amount of data ready to be sent, are transferred between the devices and/or interfaces on the card.
摘要翻译：诸如现场可编程门阵列（“FPGA”）的专用集成电路（“ASIC”）器件可以使用诸如高速多吉比特串行收发器（“MGT”）连接的串行I / O连接进行互连。例如，可以采用串行I / O连接来互连一对ASIC以产生高带宽，低信号计数连接，并且以使得单个电路卡上的任何给定的一对多个ASIC器件可以与每个ASIC通信其他通过不超过一个串行数据通信链路连接步骤。可重新配置的硬件架构（“RHA”）可以被配置为包括使用高带宽分组路由器的通信基础设施，以在可能存在于单个电路卡上的多个接口和/或多个设备之间建立标准通信协议。根据准备发送的数据量大小的动态尺寸数据包在卡上的设备和/或接口之间传送。

12. 发明授权

US08583720B2 Reconfigurable networked processing elements partial differential equations system 失效
标题翻译：可重构网络处理元件偏微分方程组
公开(公告)号：US08583720B2
公开(公告)日：2013-11-12
申请号：US12703513
申请日：2010-02-10
申请人： Antone Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna , Jerry W. Yancey
发明人： Antone Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna , Jerry W. Yancey
IPC分类号： G06F7/38 , G06F17/22
CPC分类号： G06F17/13
摘要： A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus.
摘要翻译：一种用于使用系统来计算偏微分方程（PDE）的解的方法广泛地包括以下步骤：确定所需的真实精度（TAR）以解决PDE，根据执行多个计算的TAR确定架构，解决PDE，基于解决PDE的架构来确定允许的时间（TA）和所需时间（TR），如果TR小于或等于TA则拒绝PDE，配置多个可编程设备架构，启动计算，并在满足准确性标准或TA到期时停止计算。该系统广泛地包括多个可编程设备，多个存储元件，设备总线，多个印刷电路板（PC）板以及板对板总线。

13. 发明申请

US20100161695A1 SYSTEM FOR DETERMINING MEDIAN VALUES OF VIDEO DATA 失效
标题翻译：用于确定视频数据中值的系统
公开(公告)号：US20100161695A1
公开(公告)日：2010-06-24
申请号：US12340166
申请日：2008-12-19
申请人： Matthew R. Standfield , Jim D. Allen , Juan Esteban Flores , Michael O'Neal Fox , Deepak Prasanna , Matthew P. DeLaquil
发明人： Matthew R. Standfield , Jim D. Allen , Juan Esteban Flores , Michael O'Neal Fox , Deepak Prasanna , Matthew P. DeLaquil
IPC分类号： G06F7/00 , G06F7/50 , G06F7/52
CPC分类号： G06F7/22
摘要： A system for determining the median of a plurality of data values comprises a plurality of field programmable gate arrays (FPGA), a plurality of inter FPGA links, an input router, a plurality of median modules, and a plurality of output transfer modules. Each FPGA includes a plurality of configurable logic elements and configurable storage elements from which the other components are formed. The inter FPGA link allows communication from one FPGA to another. The input router receives the plurality of data values and creates a plurality of data streams. The median module receives at least one data stream, increments a plurality of counters corresponding to a single data value within the range of data values, and determines the median by accumulating the contents of each counter. The output transfer module transfers the median to an external destination along with performance statistics of the determination of the median.
摘要翻译：用于确定多个数据值的中值的系统包括多个现场可编程门阵列（FPGA），多个FPGA间链路，输入路由器，多个中间模块和多个输出传输模块。每个FPGA包括多个可配置逻辑元件和可配置的存储元件，其中形成其它组件。 FPGA间链路允许从一个FPGA到另一个FPGA的通信。输入路由器接收多个数据值并创建多个数据流。中值模块接收至少一个数据流，在数据值的范围内增加对应于单个数据值的多个计数器，并通过累加每个计数器的内容来确定中值。输出传输模块将中值转移到外部目的地以及中位数确定的性能统计。

14. 发明授权

US08175095B2 Systems and methods for sending data packets between multiple FPGA devices 有权
标题翻译：用于在多个FPGA器件之间发送数据包的系统和方法
公开(公告)号：US08175095B2
公开(公告)日：2012-05-08
申请号：US12340094
申请日：2008-12-19
申请人： Joshua D. Anderson , Scott M. Burkart , Matthew P. DeLaquil , Deepak Prasanna
发明人： Joshua D. Anderson , Scott M. Burkart , Matthew P. DeLaquil , Deepak Prasanna
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L49/10 , H04L49/25
摘要： Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Dynamically-sized data packets, sized in accordance with the amount of data ready to be sent, are transferred between the devices and/or interfaces on the card.
摘要翻译：诸如现场可编程门阵列（“FPGA”）的专用集成电路（“ASIC”）器件可以使用诸如高速多吉比特串行收发器（“MGT”）连接的串行I / O连接进行互连。例如，可以采用串行I / O连接来互连一对ASIC以产生高带宽，低信号计数连接，并且以使得单个电路卡上的任何给定的一对多个ASIC器件可以与每个ASIC通信其他通过不超过一个串行数据通信链路连接步骤。可重新配置的硬件架构（“RHA”）可以被配置为包括使用高带宽分组路由器的通信基础设施，以在可能存在于单个电路卡上的多个接口和/或多个设备之间建立标准通信协议。根据准备发送的数据量大小的动态尺寸数据包在卡上的设备和/或接口之间传送。

15. 发明授权

US08139864B2 System for non-uniformity correction for image processing 有权
标题翻译：图像处理不均匀校正系统
公开(公告)号：US08139864B2
公开(公告)日：2012-03-20
申请号：US12340123
申请日：2008-12-19
申请人： Matthew R. Standfield , Jim D. Allen , Michael O'Neal Fox , Deepak Prasanna , Matthew P. DeLaquil
发明人： Matthew R. Standfield , Jim D. Allen , Michael O'Neal Fox , Deepak Prasanna , Matthew P. DeLaquil
IPC分类号： G06K9/46
CPC分类号： G06T5/009 , G06T2207/10016
摘要： A system for correcting image characteristic data from a plurality of pixels comprises at least one field programmable gate array (FPGA), a lookup table, and a correction module. The FPGA may include a plurality of configurable logic elements and a plurality of configurable storage elements. The lookup table may be accessible by the FPGA and may store a plurality of correction components associated with each pixel, including a gain value, an offset value, and a bad pixel value. The correction module may be formed from the configurable logic elements and configurable storage elements and may receive the characteristic data and the correction components. The correction module may generate corrected data for each characteristic data by utilizing the gain value, the offset value, and the bad pixel value.
摘要翻译：用于从多个像素校正图像特征数据的系统包括至少一个现场可编程门阵列（FPGA），查找表和校正模块。 FPGA可以包括多个可配置逻辑元件和多个可配置存储元件。查找表可以由FPGA访问，并且可以存储与每个像素相关联的多个校正分量，包括增益值，偏移值和不良像素值。校正模块可以由可配置逻辑元件和可配置存储元件形成，并且可以接收特征数据和校正组件。校正模块可以通过利用增益值，偏移值和不良像素值来生成每个特征数据的校正数据。

16. 发明申请

US20110196907A1 RECONFIGURABLE NETWORKED PROCESSING ELEMENTS PARTIAL DIFFERENTIAL EQUATIONS SYSTEM 失效
标题翻译：可重构网络处理元件部分差分方程系统
公开(公告)号：US20110196907A1
公开(公告)日：2011-08-11
申请号：US12703513
申请日：2010-02-10
申请人： Antone Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna , Jerry W. Yancey
发明人： Antone Kusmanoff , Matthew P. DeLaquil , Deepak Prasanna , Jerry W. Yancey
IPC分类号： G06F17/11
CPC分类号： G06F17/13
摘要： A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus.
摘要翻译：一种用于使用系统来计算偏微分方程（PDE）的解的方法广泛地包括以下步骤：确定所需的真实精度（TAR）以解决PDE，根据执行多个计算的TAR确定架构，解决PDE，基于解决PDE的架构来确定允许的时间（TA）和所需时间（TR），如果TR小于或等于TA则拒绝PDE，配置多个可编程设备架构，启动计算，并在满足准确性标准或TA到期时停止计算。该系统广泛地包括多个可编程设备，多个存储元件，设备总线，多个印刷电路板（PC）板以及板对板总线。

17. 发明申请

US20100169403A1 SYSTEM FOR MATRIX PARTITIONING IN LARGE-SCALE SPARSE MATRIX LINEAR SOLVERS 审中-公开
标题翻译：用于大规模稀疏矩阵线性解算器中矩阵分割的系统
公开(公告)号：US20100169403A1
公开(公告)日：2010-07-01
申请号：US12347407
申请日：2008-12-31
申请人： Matthew P. DeLaquil , Deepak Prasanna , Scott M. Burkart , Joshua D. Anderson , Aya Nagao Bennett
发明人： Matthew P. DeLaquil , Deepak Prasanna , Scott M. Burkart , Joshua D. Anderson , Aya Nagao Bennett
IPC分类号： G06F17/11 , G06F17/16
CPC分类号： G06F17/12
摘要： A system for solving large-scale matrix equations comprises a plurality of field programmable gate arrays (FPGAs), a plurality of memory elements, a plurality of memory element controllers, and a plurality of processing elements. The FPGAs may include a plurality of configurable logic elements and a plurality of configurable storage elements. The memory elements may be accessible by the FPGAs and may store a matrix and a first vector. The memory element controllers may be formed from configurable logic elements and configurable storage elements and may supply at least a portion of a row of the matrix and at least a portion of the first vector. Each processing element may receive at least the row of the matrix and the first vector and solve an iteration for one element of the first vector.
摘要翻译：用于求解大规模矩阵方程的系统包括多个现场可编程门阵列（FPGA），多个存储元件，多个存储元件控制器和多个处理元件。 FPGA可以包括多个可配置的逻辑元件和多个可配置的存储元件。存储器元件可以由FPGA访问，并且可以存储矩阵和第一向量。存储器元件控制器可以由可配置的逻辑元件和可配置的存储元件形成，并且可以提供矩阵的行的至少一部分和第一向量的至少一部分。每个处理元件可以至少接收矩阵的行和第一向量并且解决第一向量的一个元素的迭代。

18. 发明申请

US20090172052A1 TILED ARCHITECTURE FOR STATIONARY-METHOD ITERATIVE LINEAR SOLVERS 有权
标题翻译：用于静态方法迭代线性解算器的倾斜架构
公开(公告)号：US20090172052A1
公开(公告)日：2009-07-02
申请号：US11966633
申请日：2007-12-28
申请人： Matthew Pascal DeLaquil , Deepak Prasanna , Scott Michael Burkart , Joshua D. Anderson
发明人： Matthew Pascal DeLaquil , Deepak Prasanna , Scott Michael Burkart , Joshua D. Anderson
IPC分类号： G06F17/11 , G06F7/52 , G06F1/16
CPC分类号： G06F17/12
摘要： A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.
摘要翻译：一种用于求解线性方程的系统包括第一电路，其包括第一乘法模块，用于将矩阵的第一行乘以矢量变量的第一实例以产生第一乘积;以及第一线性求解器模块，用于计算更新的第一元素矢量变量使用第一个产品。第二电路包括第二乘法模块，用于将矩阵的第二行乘以矢量变量的第二实例以产生第二乘积;以及第二线性求解器模块，用于使用第二乘积来计算向量变量的更新的第二元素。接口模块使用第一更新元素更新矢量变量的第二实例，并用第二更新元素更新矢量变量的第一实例。

19. 发明授权

US08589935B2 Heterogeneous reconfigurable agent compute engine (HRACE) 失效
标题翻译：异构可重配置代理计算引擎（HRACE）
公开(公告)号：US08589935B2
公开(公告)日：2013-11-19
申请号：US11745558
申请日：2007-05-08
申请人： Deepak Prasanna , Gerald L. Fudge
发明人： Deepak Prasanna , Gerald L. Fudge
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F9/52 , G06F9/5072 , Y02D10/22 , Y02D10/36
摘要： A computing system (10) includes a plurality of hardware computing resources (12-36) controlled at least in part by a plurality of autonomous computing agents (40,42,44). Each autonomous computing agent (40,42,44) includes or has access to operating information including processing information (46), resource information (48), optimization information (50), and communication information (52). The computing agents (40,42,44) collaborate to optimize performance of the system (10) and to assign computing tasks to the resources (12-36) according to a predetermined strategy. The predetermined strategy may seek to optimize speed, power, or communication efficiency of the system 10. Each agent (40,42,44) may optimize performance of the system (10) by assigning tasks to best-fit resources or by reconfiguring one or more resources. The agents (40,42,44) may collaborate to optimize performance of the system (10) by sharing resource and task information and assigning tasks to best-fit resources based on the shared information, reconfiguring one or more resources based on the shared information, or both.
摘要翻译：计算系统（10）包括至少部分由多个自主计算代理（40,42,44）控制的多个硬件计算资源（12-36）。每个自主计算代理（40,42,44）包括或可以访问包括处理信息（46），资源信息（48），优化信息（50）和通信信息（52）的操作信息。计算代理（40,42,44）协作以优化系统（10）的性能并根据预定策略将计算任务分配给资源（12-36）。预定策略可以寻求优化系统10的速度，功率或通信效率。每个代理（40,42,44）可以通过将任务分配给最适合资源来优化系统（10）的性能，或者通过重新配置一个或更多资源。代理（40,42,44）可以通过共享资源和任务信息并基于共享信息将任务分配给最佳拟合资源来协作来优化系统（10）的性能，基于共享信息重新配置一个或多个资源，或两者。

20. 发明授权

US08166090B2 Tiled architecture for stationary-method iterative linear solvers 有权
标题翻译：用于固定方法迭代线性求解器的平铺架构
公开(公告)号：US08166090B2
公开(公告)日：2012-04-24
申请号：US11966633
申请日：2007-12-28
申请人： Matthew Pascal DeLaquil , Deepak Prasanna , Scott Michael Burkart , Joshua D. Anderson , Antone Lee Kusmanoff
发明人： Matthew Pascal DeLaquil , Deepak Prasanna , Scott Michael Burkart , Joshua D. Anderson , Antone Lee Kusmanoff
IPC分类号： G06F7/38
CPC分类号： G06F17/12
摘要： A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.
摘要翻译：一种用于求解线性方程的系统包括第一电路，其包括第一乘法模块，用于将矩阵的第一行乘以矢量变量的第一实例以产生第一乘积;以及第一线性求解器模块，用于计算更新的第一元素矢量变量使用第一个产品。第二电路包括第二乘法模块，用于将矩阵的第二行乘以矢量变量的第二实例以产生第二乘积;以及第二线性求解器模块，用于使用第二乘积来计算向量变量的更新的第二元素。接口模块使用第一更新元素更新矢量变量的第二实例，并用第二更新元素更新矢量变量的第一实例。

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