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11. 发明授权

US08194780B2 Differential signal output device 有权
标题翻译：差分信号输出装置
公开(公告)号：US08194780B2
公开(公告)日：2012-06-05
申请号：US12222523
申请日：2008-08-11
申请人： Nobunari Tsukamoto , Hidetoshi Ema
发明人： Nobunari Tsukamoto , Hidetoshi Ema
IPC分类号： H04B14/06
CPC分类号： G06F13/4291
摘要： A differential signal output device is disclosed that outputs transmission data as a differential signal. The device includes a first differential signal generation circuit that amplifies a signal representing the transmission data and generates the differential signal from the amplified signal; a dummy data generation circuit that is synchronized with a reference clock of the transmission data and generates dummy data that change only in a bit where the transmission data do not change; and a second differential signal generation circuit that amplifies a signal representing the dummy data and generates another differential signal from the amplified signal.
摘要翻译：公开了一种输出传输数据作为差分信号的差分信号输出装置。该装置包括：第一差分信号生成电路，其放大表示发送数据的信号，并从放大信号生成差分信号; 与发送数据的基准时钟同步的伪数据生成电路，生成仅在发送数据不发生变化的比特中变化的伪数据; 以及第二差分信号生成电路，其对表示所述虚拟数据的信号进行放大，并从所述放大信号生成另一差分信号。

12. 发明授权

US08023605B2 Oversampling circuit and oversampling method 有权
标题翻译：过采样电路和过采样方法
公开(公告)号：US08023605B2
公开(公告)日：2011-09-20
申请号：US11845416
申请日：2007-08-27
申请人： Nobunari Tsukamoto , Hidetoshi Ema
发明人： Nobunari Tsukamoto , Hidetoshi Ema
IPC分类号： H04L7/00
CPC分类号： H04L7/0338
摘要： A multiphase delay unit causes different delay times to a reference clock to generate a multiphase clock with different phases. A multiphase sampling unit samples the input signal using the multiphase clock, and outputs multiphase sampling data. A phase selecting unit detects a phase relation of the multiphase clock using the multiphase sampling data, and selects output data from the multiphase sampling data based on a result of detecting the phase relation.
摘要翻译：多相延迟单元对参考时钟产生不同的延迟时间以产生具有不同相位的多相时钟。多相采样单元使用多相时钟采样输入信号，并输出多相采样数据。相位选择单元使用多相采样数据检测多相时钟的相位关系，并且基于检测相位关系的结果从多相采样数据中选择输出数据。

13. 发明申请

US20080143814A1 Pixel Clock Generator, Pulse Modulator, and Image Forming Apparatus 有权
标题翻译：像素时钟发生器，脉冲调制器和图像形成装置
公开(公告)号：US20080143814A1
公开(公告)日：2008-06-19
申请号：US11793594
申请日：2006-04-20
申请人： Naruhiro Masui , Hidetoshi Ema , Nobunari Tsukamoto
发明人： Naruhiro Masui , Hidetoshi Ema , Nobunari Tsukamoto
IPC分类号： B41J2/435
CPC分类号： G02B26/127 , G06K15/1219 , H04N1/0473 , H04N2201/0082 , H04N2201/04755 , H04N2201/04791 , H04N2201/04794
摘要： A comparator compares a time interval between a first synchronization signal and a second synchronization signal with a target value, and outputs an error therebetween. A frequency calculator calculates a set value of a pixel clock frequency based on the error output from the comparator, and outputs a frequency specification signal for specifying a pixel clock frequency according to the calculated set value. A frequency divider divides a high frequency clock generated by a high frequency clock generator by a frequency division ratio based on the frequency specification signal output from the frequency calculator, and generates the pixel clock.
摘要翻译：比较器将第一同步信号和第二同步信号之间的时间间隔与目标值进行比较，并在其间输出误差。频率计算器基于从比较器输出的误差来计算像素时钟频率的设定值，并根据计算出的设定值输出用于指定像素时钟频率的频率指定信号。分频器基于从频率计算器输出的频率指定信号，通过分频比将由高频时钟发生器产生的高频时钟分频，并生成像素时钟。

14. 发明授权

US10298419B2 Low voltage differential signaling driver 有权
公开(公告)号：US10298419B2
公开(公告)日：2019-05-21
申请号：US15795927
申请日：2017-10-27
申请人： Yuji Watabe , Hiroaki Kyogoku , Nobunari Tsukamoto
发明人： Yuji Watabe , Hiroaki Kyogoku , Nobunari Tsukamoto
IPC分类号： H03L5/00 , H04L25/02 , H03K19/0185 , H03K17/687 , H03L7/093 , G06F1/06 , H03K5/135 , H03L7/081
摘要： A low voltage differential signaling driver includes at least one output circuit, a first control circuit, and a second control circuit. The output circuit includes a first input terminal to receive a first input signal, a second input terminal to receive a second input signal, a first output terminal to output a first output signal, a second output terminal to output a second output signal, and first to sixth transistors. The first control circuit controls a voltage of a control terminal of the first transistor to make a voltage of the first output signal equal to a first reference voltage when the first input signal has a first value. The second control circuit controls a voltage of a control terminal of the second transistor to make the voltage of the first output signal equal to a second reference voltage when the first input signal has a second value.

15. 发明授权

US09684808B2 Wireless communication apparatus and mobile device 有权
公开(公告)号：US09684808B2
公开(公告)日：2017-06-20
申请号：US15064300
申请日：2016-03-08
申请人： Nobunari Tsukamoto , Masaaki Tsuji , Koji Kawahata , Yuusuke Kudoh
发明人： Nobunari Tsukamoto , Masaaki Tsuji , Koji Kawahata , Yuusuke Kudoh
IPC分类号： H04B5/00 , G06K7/10 , H04M1/725 , H04B1/48
CPC分类号： G06K7/10237 , G06K7/10158 , H04B1/48 , H04B5/0031 , H04B5/0056 , H04B5/0062 , H04M1/7253 , H04M2250/04
摘要： A wireless communication apparatus includes an amplifier circuit configured to amplify a signal output by a wireless communication unit that executes wireless communication, to output the signal having amplified to a transceiver unit; and a decision unit configured to decide, based on an operational mode of the wireless communication unit, whether to transmit the signal from the transceiver unit via the amplifier circuit, or transmit the signal from the transceiver unit without going via the amplifier circuit.

16. 发明授权

US09407312B2 Amplifier circuit, antenna module and wireless communication apparatus 有权
标题翻译：放大器电路，天线模块和无线通信装置
公开(公告)号：US09407312B2
公开(公告)日：2016-08-02
申请号：US14428238
申请日：2013-09-11
申请人： Masaaki Tsuji , Kohji Kawahata , Nobunari Tsukamoto , Naohiro Itoh
发明人： Masaaki Tsuji , Kohji Kawahata , Nobunari Tsukamoto , Naohiro Itoh
IPC分类号： H04B15/00 , H04B1/40 , G06K19/07 , H03D1/00 , H04B5/00 , H03F3/19 , H04B1/3827 , H04B1/04
CPC分类号： H04B1/40 , G06K19/0723 , G06K19/0726 , H03D1/00 , H03F3/19 , H03F3/24 , H03F2200/451 , H04B1/3827 , H04B5/0031 , H04B5/0056 , H04B15/00 , H04B2001/0408
摘要： An amplifier circuit that amplifies a carrier wave that a transmitting and receiving part has received, and includes a superimposition wave generation part that generates a superimposition wave to be superimposed onto the carrier wave; an amplifying part that adds the carrier wave and the superimposition wave to obtain an amplified carrier wave and outputs the amplified carrier wave; and an amplitude detection part that detects, based on a change in an amplitude value of the carrier wave, that the carrier wave is a predetermined carrier wave that carries a predetermined communication signal. The amplifier circuit outputs the amplified carrier wave when having detected the predetermined carrier wave.
摘要翻译：放大电路，放大发送和接收部分已经接收到的载波，并且包括产生叠加在载波上的叠加波的叠加波产生部分; 放大部分，其加载载波和叠加波以获得放大的载波并输出放大的载波; 以及振幅检测部，其基于载波的振幅值的变化来检测载波是携带预定通信信号的预定载波。当检测到预定的载波时，放大器电路输出放大的载波。

17. 发明授权

US07791634B2 Pixel clock generator, pulse modulator, and image forming apparatus 有权
标题翻译：像素时钟发生器，脉冲调制器和图像形成装置
公开(公告)号：US07791634B2
公开(公告)日：2010-09-07
申请号：US11793594
申请日：2006-04-20
申请人： Naruhiro Masui , Hidetoshi Ema , Nobunari Tsukamoto
发明人： Naruhiro Masui , Hidetoshi Ema , Nobunari Tsukamoto
IPC分类号： B41J2/435
CPC分类号： G02B26/127 , G06K15/1219 , H04N1/0473 , H04N2201/0082 , H04N2201/04755 , H04N2201/04791 , H04N2201/04794
摘要： A comparator compares a time interval between a first synchronization signal and a second synchronization signal with a target value, and outputs an error therebetween. A frequency calculator calculates a set value of a pixel clock frequency based on the error output from the comparator, and outputs a frequency specification signal for specifying a pixel clock frequency according to the calculated set value. A frequency divider divides a high frequency clock generated by a high frequency clock generator by a frequency division ratio based on the frequency specification signal output from the frequency calculator, and generates the pixel clock.
摘要翻译：比较器将第一同步信号和第二同步信号之间的时间间隔与目标值进行比较，并在其间输出误差。频率计算器基于从比较器输出的误差来计算像素时钟频率的设定值，并根据计算出的设定值输出用于指定像素时钟频率的频率指定信号。分频器基于从频率计算器输出的频率指定信号，通过分频比将由高频时钟发生器产生的高频时钟分频，并生成像素时钟。

18. 发明申请

US20070297548A1 DATA PROCESSING APPARATUS 有权
标题翻译：数据处理设备
公开(公告)号：US20070297548A1
公开(公告)日：2007-12-27
申请号：US11763663
申请日：2007-06-15
申请人： Nobunari Tsukamoto , Hidetoshi Ema
发明人： Nobunari Tsukamoto , Hidetoshi Ema
IPC分类号： H04L7/00
CPC分类号： H03M7/3048
摘要： A disclosed data processing apparatus includes: a binarization unit binarizing input data based on a threshold voltage; a capture unit capturing data from a binary output binarized by the binarization unit; a duty cycle detection unit detecting a duty cycle of the binary output; and a control unit controlling a level of the input data based on the duty cycle detected by the duty cycle detection unit.
摘要翻译：公开的数据处理装置包括：二值化单元，基于阈值电压二值化输入数据; 捕获单元，从由二值化单元二值化的二进制输出中获取数据; 占空比检测单元，检测二进制输出的占空比; 以及控制单元，其基于由占空比检测单元检测到的占空比来控制输入数据的电平。

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