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11. 发明申请

US20070114597A1 Twin insulator charge storage device operation and its fabrication method 有权
标题翻译：双绝缘子电荷存储装置的操作及其制作方法
公开(公告)号：US20070114597A1
公开(公告)日：2007-05-24
申请号：US11652888
申请日：2007-01-12
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： H01L29/792
CPC分类号： G11C16/0475 , G11C16/0483 , G11C16/14 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/792
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.
摘要翻译：本发明提出了改进的双MONOS存储器件及其制造方法。 ONO层水平自对准控制门。控制栅极和字栅之间的垂直绝缘体不包括氮化物层。这样可以防止电子捕获的问题。可以制造器件以通过ONO绝缘体的顶部或底部氧化物层拉出电子。该器件还包括在控制栅极之间的升高的存储器位扩散以减小位阻。双MONOS存储器阵列可以通过本发明的方法嵌入到标准CMOS电路中。

12. 发明授权

US07149126B2 Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory 有权
标题翻译：用于制作和编程并操作双位多级弹道MONOS存储器的过程
公开(公告)号：US07149126B2
公开(公告)日：2006-12-12
申请号：US10756568
申请日：2004-01-13
申请人： Seiki Ogura , Yutaka Hayashi , Tomoko Ogura
发明人： Seiki Ogura , Yutaka Hayashi , Tomoko Ogura
IPC分类号： G11C16/04
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L27/115
摘要： A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.
摘要翻译：描述了一种快速低电压弹道程序，超短通道，超高密度双位多级闪存。本发明的结构和操作通过具有小于40nm的超短控制栅极通道的双重MONOS单元结构实现，具有提供高电子注入效率的弹道注入和在3〜5V的低编程电压下非常快速的程序。弹道MONOS存储单元被布置在以下阵列中：每个存储单元包含用于一个字门的两个氮化物区域，以及1/2扩散源和1/2位扩散。控制门可以单独定义，也可以通过相同的扩散共享。扩散在单元之间共享并且平行于侧壁控制栅极并垂直于字线。

13. 发明授权

US06982456B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
公开(公告)号：US06982456B2
公开(公告)日：2006-01-03
申请号：US10889013
申请日：2004-07-13
申请人： Nobuyo Sugiyama , Hiromasa Fujimoto , Shinji Odanaka , Seiki Ogura
发明人： Nobuyo Sugiyama , Hiromasa Fujimoto , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween. Within the semiconductor substrate and in the vicinity of the stepped portion, there is formed a depletion control layer which is composed of a heavily doped impurity region and formed to extend from a position located under the floating gate electrode and at a distance from the upper corner of the stepped portion toward the lower corner of the stepped portion and adjoin the end portion of a drain region without reaching a step side region.

14. 发明授权

US06770931B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
公开(公告)号：US06770931B2
公开(公告)日：2004-08-03
申请号：US10366420
申请日：2003-02-14
申请人： Nobuyo Sugiyama , Hiromasa Fujimoto , Shinji Odanaka , Seiki Ogura
发明人： Nobuyo Sugiyama , Hiromasa Fujimoto , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween. Within the semiconductor substrate and in the vicinity of the stepped portion, there is formed a depletion control layer which is composed of a heavily doped impurity region and formed to extend from a position located under the floating gate electrode and at a distance from the upper corner of the stepped portion toward the lower corner of the stepped portion and adjoin the end portion of a drain region without reaching a step side region.

15. 发明授权

US06707079B2 Twin MONOS cell fabrication method and array organization 有权
标题翻译：双MONOS电池制造方法和阵列组织
公开(公告)号：US06707079B2
公开(公告)日：2004-03-16
申请号：US10356446
申请日：2003-02-03
申请人： Kumihiro Satoh , Seiki Ogura , Tomoya Saito
发明人： Kumihiro Satoh , Seiki Ogura , Tomoya Saito
IPC分类号： H01L2976
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , H01L29/66833 , H01L29/7923 , Y10S257/906 , Y10S438/954
摘要： Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit. The invention consists of two fabrication methods, i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication. ii) Bit line crosses word gate and control gate. The invention focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two shared control gates on both sidewalls of a select gate. The method is applicable to a device with a flat channel and/or a device having a step channel. Two embodiments of the present invention are disclosed.
摘要翻译：在本发明中提出了一种用于集成双MONOS存储单元阵列和CMOS逻辑器件电路的高密度双MONOS存储器件的制造方法及其阵列组织。本发明由两种制造方法组成：i）同时定义存储器栅极和逻辑门，从而改进工艺集成方案，以便更容易和更可靠的制造.ii）位线跨越字门和控制栅极。本发明着重于降低寄生薄片电阻以实现高速同时保持低的制造成本。双MONOS单元将存储器存储在选择栅极的两个侧壁上的两个共享控制栅极下的两个氮化物存储单元元件中。该方法适用于具有平坦通道的设备和/或具有步进通道的设备。本发明的两个实施例被公开。

16. 发明授权

US06636439B1 Fast program to program verify method 有权
公开(公告)号：US06636439B1
公开(公告)日：2003-10-21
申请号：US10371840
申请日：2003-02-20
申请人： Seiki Ogura , Tomoko Ogura , Nori Ogura
发明人： Seiki Ogura , Tomoko Ogura , Nori Ogura
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C16/0475 , G11C16/12 , G11C16/3454
摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

17. 发明授权

US06558997B2 Method for fabricating the control and floating gate electrodes without having their upper surface silicided 有权
标题翻译：制造控制和浮栅电极而不使其上表面硅化的方法
公开(公告)号：US06558997B2
公开(公告)日：2003-05-06
申请号：US09942948
申请日：2001-08-31
申请人： Fumihiko Noro , Seiki Ogura
发明人： Fumihiko Noro , Seiki Ogura
IPC分类号： H01L218238
CPC分类号： H01L27/11526 , G11C16/0425 , H01L27/115 , H01L27/11543
摘要： A semiconductor memory has first and second active regions that have been defined in a semiconductor substrate and electrically isolated from each other. Over the first active region, a control gate electrode has been formed with a control gate insulating film interposed therebetween. A floating gate electrode has been formed adjacent to a side face of the control gate electrode with a capacitive insulating film interposed therebetween. A tunnel insulating film is interposed between the first active region and the floating gate electrode. A gate electrode has been formed over the second active region with a gate insulating film interposed therebetween. Source/drain regions have been defined in respective parts of the second active region beside the gate electrode. Only the source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.
摘要翻译：半导体存储器具有已经限定在半导体衬底中并且彼此电隔离的第一和第二有源区。在第一有源区域之后，形成控制栅极电极，其间插入有控制栅极绝缘膜。已经在控制栅极的侧面附近形成有浮置栅电极，其间插入有电容绝缘膜。隧道绝缘膜介于第一有源区和浮栅之间。在第二有源区上形成有栅极电极，其间插入有栅极绝缘膜。在栅电极旁边的第二有源区的相应部分中限定了源极/漏极区。只有源极/漏极区域和栅极电极的上表面被金属硅化物膜覆盖。

18. 发明授权

US06549463B2 Fast program to program verify method 有权
公开(公告)号：US06549463B2
公开(公告)日：2003-04-15
申请号：US10016916
申请日：2001-12-14
申请人： Seiki Ogura , Tomoko Ogura , Nori Ogura
发明人： Seiki Ogura , Tomoko Ogura , Nori Ogura
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C16/0475 , G11C16/12 , G11C16/3454
摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

19. 发明授权

US06542412B2 Process for making and programming and operating a dual-bit multi-level ballistic flash memory 有权
标题翻译：制造和编程和操作双位多级弹道闪存的过程
公开(公告)号：US06542412B2
公开(公告)日：2003-04-01
申请号：US10058484
申请日：2002-01-28
申请人： Seiki Ogura , Tomoko Ogura
发明人： Seiki Ogura , Tomoko Ogura
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C11/5621 , G11C16/0425 , G11C16/0475 , G11C16/0491 , H01L27/115 , H01L27/11524
摘要： A fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables low voltage requirement on the floating gate during erase is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular to both the bit lines and control gate lines. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow erase access to the individual floating gate.
摘要翻译：一种快速程序，超高密度，双位，多级闪存过程，可应用于弹道分割栅侧壁晶体管，或可应用于弹道平面分裂栅侧壁晶体管，可实现低电压要求在擦除时在浮动栅上进行描述。两个侧壁浮动栅极与单个字线选择栅极配对，并且字线被布置成垂直于位线和控制栅极线。相同字线上的相邻存储单元共享位线扩散以及第三个多路控制门。控制门允许擦除访问各个浮动门。

20. 发明授权

US06184553B2 Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device 失效
公开(公告)号：US06184553B2
公开(公告)日：2001-02-06
申请号：US09325772
申请日：1999-06-04
申请人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
发明人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
IPC分类号： H07L27115
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

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