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11. 发明申请

US20050207228A1 Semiconductor integrated circuit and magnetic storage device using the same 失效
标题翻译：半导体集成电路和使用其的磁存储器件
公开(公告)号：US20050207228A1
公开(公告)日：2005-09-22
申请号：US11030067
申请日：2005-01-07
申请人： Hiroki Yamashita , Masayoshi Yagyu , Fumio Yuuki , Tatsuya Kawashimo
发明人： Hiroki Yamashita , Masayoshi Yagyu , Fumio Yuuki , Tatsuya Kawashimo
IPC分类号： G11B5/09 , G11B5/00 , G11B5/012 , G11B5/02 , G11B5/39 , G11C16/06 , H03K17/00 , H03K17/687
CPC分类号： G11B5/02 , B82Y10/00 , B82Y25/00 , G11B5/022 , G11B2005/0013 , G11B2005/3996 , H03K17/6872 , H03K2217/0036
摘要： The present invention provides a semiconductor integrated circuit capable of reducing a circuit area and a magnetic storage device using the same. The circuit in the present invention is provided with a single-stage output transistor for supplying write current to a magnetic head, a current source for outputting reference current of the write current, a diode-connected NMOS transistor for converting the current to gate voltage and having a certain device size ratio to the output transistor, a regulator circuit for transmitting gate voltage of the NMOS transistor and reducing output impedance, and a CMOS circuit for setting power supply voltage to an output of the regulator circuit and controlling the gate voltage of the output transistor. Then, this circuit is applied as a write circuit in a magnetic storage device.
摘要翻译：本发明提供能够减少电路面积的半导体集成电路和使用该半导体集成电路的磁存储装置。本发明的电路设置有用于向磁头提供写入电流的单级输出晶体管，用于输出写入电流的参考电流的电流源，用于将电流转换为栅极电压的二极管连接的NMOS晶体管，以及与输出晶体管具有一定的器件尺寸比，用于传输NMOS晶体管的栅极电压并降低输出阻抗的调节器电路，以及用于将电源电压设置到调节器电路的输出并控制调节器电路的栅极电压的CMOS电路输出晶体管。然后，该电路作为写入电路应用于磁存储装置。

12. 发明申请

US20050174190A1 Connection structure of high frequency lines and optical transmission module using the connection structure 审中-公开
标题翻译：高频线连接结构和光传输模块采用连接结构
公开(公告)号：US20050174190A1
公开(公告)日：2005-08-11
申请号：US10628234
申请日：2003-07-29
申请人： Masayoshi Yagyu , Tatsuya Saito , Shigeo Oomae , Mitsuo Akashi
发明人： Masayoshi Yagyu , Tatsuya Saito , Shigeo Oomae , Mitsuo Akashi
IPC分类号： H01P5/08
CPC分类号： H01P5/08
摘要： A connection structure is applied to mutually connect a first and a second transmission line that is planar in shape and that has a ground conductor on a second main surface, such as a microstrip line or a coplanar line with a ground. The first and the second transmission lines are superposed one upon the other, and their signal wiring patterns are electrically connected, as are their ground conductors. An end surface of the first transmission line is substantially covered by a conductor layer connected to the ground conductor. The connection structure can achieve good signal transmission characteristics up to high-frequency bands on the order of several tens of gigahertz.
摘要翻译：应用连接结构来相互连接形状为平面的第一和第二传输线，并且在诸如微带线或与地面的共面线之类的第二主表面上具有接地导体。第一和第二传输线彼此重叠，并且它们的信号布线图形与它们的接地导体一样电连接。第一传输线的端面基本上被连接到接地导体的导体层覆盖。连接结构可以达到高达几十千兆赫兹的高频带的良好的信号传输特性。

13. 发明授权

US08358708B2 Low offset input circuit and transmission system with the input circuit 有权
公开(公告)号：US08358708B2
公开(公告)日：2013-01-22
申请号：US12453980
申请日：2009-05-28
申请人： Takashi Takemoto , Hiroki Yamashita , Masayoshi Yagyu
发明人： Takashi Takemoto , Hiroki Yamashita , Masayoshi Yagyu
IPC分类号： H04L7/00
CPC分类号： H03F3/45475 , H03F3/24 , H03F3/3028 , H03F3/45183 , H03F3/45605 , H03F3/45977 , H03F2200/411 , H03F2200/537 , H03F2203/45212 , H03F2203/45674 , H03F2203/45702 , H03F2203/45726
摘要： A low offset input circuit and a signal transmission system which can accommodate a high-speed interface and achieve reduction of an offset voltage are provided. An offset voltage compensating circuit block 103 having an input circuit block 108 including an input circuit 104 and an adder-subtractor circuit block 105, switches 108, 109, a detecting circuit block 106, and an adjusting and holding circuit block 107 is provided. To compensate for an offset voltage of the input circuit block 102, an offset voltage of the input circuit block 102 is detected at the detecting circuit block 106 by turning on the switches 108, 109, and the detected offset voltage is held in the adjusting and holding circuit block 107, and negative feedback of the held offset voltage to the adder-subtractor circuit block 105 is performed. Thereby, signals Vop, Von having compensated offset voltages are outputted from the input circuit block 102.

14. 发明授权

US07768330B2 Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US07768330B2
公开(公告)日：2010-08-03
申请号：US12003443
申请日：2007-12-26
申请人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Koji Fukuda
发明人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Koji Fukuda
IPC分类号： H03K3/00
CPC分类号： H03K3/356191 , H03K3/356139 , H03K3/3562 , H03M9/00
摘要： For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.
摘要翻译：例如，在包括具有差分放大器配置的数据采集部分的逻辑电路中提供增益控制部分和公共节点控制部分，并且当点击信号为“H”电平时获取数据输入信号，并且锁存部分当点击信号为“L”电平时，锁存来自数据采集部分的数据输出信号。增益控制部分设置在差分放大器中的NMOS晶体管的公共节点之间，用于使高频带中差分放大器的增益高于低频带。当时钟信号为“L”电平时，公共节点控制部分用于控制电荷，以消除公共节点之间的电位差。因此，数据输出信号的转换时间被加速并且在锁存部分中增加了设置余量。因此，上述技术可以加速诸如锁存电路的各种逻辑电路的操作。

15. 发明申请

US20080204100A1 Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US20080204100A1
公开(公告)日：2008-08-28
申请号：US12003443
申请日：2007-12-26
申请人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Koji Fukuda
发明人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Koji Fukuda
IPC分类号： H03K3/289 , H03K3/286
CPC分类号： H03K3/356191 , H03K3/356139 , H03K3/3562 , H03M9/00
摘要： For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.
摘要翻译：例如，在包括具有差分放大器配置的数据采集部分的逻辑电路中提供增益控制部分和公共节点控制部分，并且当点击信号为“H”电平时获取数据输入信号，并且锁存部分当点击信号为“L”电平时，锁存来自数据采集部分的数据输出信号。增益控制部分设置在差分放大器中的NMOS晶体管的公共节点之间，用于使高频带中差分放大器的增益高于低频带。当时钟信号为“L”电平时，公共节点控制部分用于控制电荷，以消除公共节点之间的电位差。因此，数据输出信号的转换时间被加速并且在锁存部分中增加了设置余量。因此，上述技术可以加速诸如锁存电路的各种逻辑电路的操作。

16. 发明授权

US07277643B2 Clock extracting fabric in a communication device 失效
标题翻译：在通信设备中的时钟提取结构
公开(公告)号：US07277643B2
公开(公告)日：2007-10-02
申请号：US10629755
申请日：2003-07-30
申请人： Takashige Baba , Tatsuya Saito , Masayoshi Yagyu , Shigeo Oomae
发明人： Takashige Baba , Tatsuya Saito , Masayoshi Yagyu , Shigeo Oomae
IPC分类号： H04B10/00 , H04L27/00 , H04L12/50 , H04J3/06
CPC分类号： H04L25/14 , H04L7/033
摘要： A signal communication apparatus of a clock reproduction system in which clock signals are extracted from each of parallel data signals for redigitizing each of the data signals. The apparatus includes a reference clock signal generating circuit which is comprised of a clock extraction circuit for extracting a clock signal from each of a plurality of bits of received data signals, and a clock signal selection circuit for selecting one of the extracted clock signals. Alternatively, the reference clock signal generating circuit may be comprised of a data signal selection circuit for selecting one of a plurality of received data signals, and a clock extraction circuit for extracting a clock signal from the selected bit. Based on the resultant reference clock signal, clock signals are obtained that are phase-adjusted for redigitizing each bit of the received data signals. The selection made in the selection circuit is switched on the basis of the output of a clock signal monitoring circuit that detects the occurrence of abnormalities in the frequency of the extracted clock signal. Thus, the extraction of clock can be continued using other bits in the event of an abnormality in the bit from which the clock is being extracted.
摘要翻译：一种时钟再现系统的信号通信装置，其中从每个并行数据信号中提取时钟信号，以对每个数据信号进行重新排序。该装置包括一个参考时钟信号产生电路，它包括一个时钟提取电路，用于从接收的数据信号的多个比特中提取一个时钟信号;以及时钟信号选择电路，用于选择所提取的时钟信号之一。或者，参考时钟信号发生电路可以包括用于选择多个接收数据信号中的一个的数据信号选择电路和用于从所选位提取时钟信号的时钟提取电路。基于所得到的参考时钟信号，获得相位调整的时钟信号，以对接收到的数据信号的每一位进行重新编码。在选择电路中进行的选择是基于检测提取的时钟信号的频率异常的发生的时钟信号监视电路的输出而被切换的。因此，在提取时钟的位的异常的情况下，可以使用其他位继续提取时钟。

17. 发明申请

US20060082422A1 Connection structure of high frequency lines and optical transmission module using the connection structure 审中-公开
标题翻译：高频线连接结构和光传输模块采用连接结构
公开(公告)号：US20060082422A1
公开(公告)日：2006-04-20
申请号：US11240455
申请日：2005-10-03
申请人： Masayoshi Yagyu , Tatsuya Saito , Shigeo Oomae , Mitsuo Akashi
发明人： Masayoshi Yagyu , Tatsuya Saito , Shigeo Oomae , Mitsuo Akashi
IPC分类号： H03H7/38
CPC分类号： H01P5/08
摘要： A connection structure is applied to mutually connect a first and a second transmission line that is planar in shape and that has a ground conductor on a second main surface, such as a microstrip line or a coplanar line with a ground. The first and the second transmission lines are superposed one upon the other, and their signal wiring patterns are electrically connected, as are their ground conductors. An end surface of the first transmission line is substantially covered by a conductor layer connected to the ground conductor. The connection structure can achieve good signal transmission characteristics up to high-frequency bands on the order of several tens of gigahertz.
摘要翻译：应用连接结构来相互连接形状为平面的第一和第二传输线，并且在诸如微带线或与地面的共面线之类的第二主表面上具有接地导体。第一和第二传输线彼此重叠，并且它们的信号布线图形与它们的接地导体一样电连接。第一传输线的端面基本上被连接到接地导体的导体层覆盖。连接结构可以达到高达几十千兆赫兹的高频带的良好的信号传输特性。

18. 发明授权

US4748494A Lead arrangement for reducing voltage variation 失效
标题翻译：用于降低电压变化的引线排列
公开(公告)号：US4748494A
公开(公告)日：1988-05-31
申请号：US853929
申请日：1986-04-21
申请人： Toshio Yamada , Hiroyuki Itho , Masayoshi Yagyu , Akira Masaki
发明人： Toshio Yamada , Hiroyuki Itho , Masayoshi Yagyu , Akira Masaki
IPC分类号： H01L21/822 , G11C11/401 , G11C11/407 , H01L21/8222 , H01L23/528 , H01L27/04 , H01L27/082 , H01L29/52 , H01L27/10
CPC分类号： H01L23/5286 , H01L2924/0002
摘要： A semiconductor device includes a plurality of circuit groups constituting an integrated circuit and each constituted by a plurality of circuit blocks and a bias circuit which applies a bias potential to said circuit blocks. The device further includes a plurality of power buses provided above the circuit groups through an insulating layer so as to feed power to circuit elements in the circuit groups. At least one of the power buses is constituted by a first bus for feeding power to the circuit groups and a plurality of second buses respectively provided for the circuit groups so that each second bus receives power from the first bus and feeds power to circuit elements in the corresponding circuit group. Each of the second buses is connected to the first bus at a predetermined position on the corresponding circuit group.
摘要翻译：半导体器件包括构成集成电路的多个电路组，并且各个电路组由多个电路块和向所述电路块施加偏置电位的偏置电路构成。该装置还包括多个电源总线，其通过绝缘层设置在电路组之上，以便向电路组中的电路元件供电。电力总线中的至少一个由用于向电路组供电的第一总线和分别为电路组提供的多个第二总线构成，使得每个第二总线从第一总线接收电力并将电力馈送到电路元件相应的电路组。每个第二总线在相应电路组上的预定位置连接到第一总线。

19. 发明授权

US08284872B2 Burst mode receiver 失效
标题翻译：突发模式接收器
公开(公告)号：US08284872B2
公开(公告)日：2012-10-09
申请号：US12687184
申请日：2010-01-14
申请人： Jun Sugawa , Hiroki Ikeda , Masayoshi Yagyu
发明人： Jun Sugawa , Hiroki Ikeda , Masayoshi Yagyu
IPC分类号： H04L27/00
CPC分类号： H04L7/0083
摘要： A burst mode receiver including a CDR circuit that does not perform bit synchronization determination at a wrong position even when a burst signal waveform containing a distortion is input is provided. The burst mode receiver includes a CDR circuit for reproducing clock and data from a received signal, a bit synchronization determination circuit for determining whether the CDR circuit is in an optimum phase, a waveform distortion determination circuit for determining from the received signal whether there is waveform distortion, and a CDR output enable determination circuit for determining whether an output of the CDR circuit is valid or invalid. The CDR output enable determination circuit performs CDR output enable determination based on a bit synchronization determination result and a waveform distortion determination result.
摘要翻译：提供了包括即使当输入包含失真的脉冲串信号波形时也不在错误位置执行位同步确定的CDR电路的突发模式接收机。突发模式接收机包括用于从接收信号再现时钟和数据的CDR电路，用于确定CDR电路是否处于最佳相位的位同步确定电路，用于根据接收信号确定是否存在波形的波形失真确定电路失真和用于确定CDR电路的输出是有效还是无效的CDR输出使能确定电路。 CDR输出使能判定电路基于位同步判定结果和波形失真判定结果进行CDR输出使能判定。

20. 发明授权

US07417818B2 Magnetic recording device 失效
标题翻译：磁记录装置
公开(公告)号：US07417818B2
公开(公告)日：2008-08-26
申请号：US11342828
申请日：2006-01-31
申请人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Tatsuya Kawashimo
发明人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Tatsuya Kawashimo
IPC分类号： G11B5/02
CPC分类号： G11B5/486 , G11B5/484
摘要： A magnetic recording device capable of reducing the size of a writing circuit and the power consumption by readily adjusting the overshoot of the write current pulses is provided. Two or more transmission lines having different characteristic impedances are provided between an output driver having an impedance Zs and a magnetic head, the transmission lines are formed so that the characteristic impedances Z1, Zn−1, and Zn (n≧2) thereof on the output driver side are higher than those on the magnetic recording head side (Z1>Zn−1>Zn), and the impedance Zs of the output driver is equal to or higher than the characteristic impedance Z1 of the transmission line.
摘要翻译：提供了能够通过容易地调整写入电流脉冲的过冲来减小写入电路的尺寸和功耗的磁记录装置。具有不同特性阻抗的两条或更多条传输线被提供在具有阻抗Z S s的输出驱动器和磁头之间，传输线形成为使得特性阻抗Z 1 = 2）高于磁记录头侧（Z _{1 。}

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