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11. 发明授权

US07205795B2 Semiconductor device having universal logic cell 有权
标题翻译：具有通用逻辑单元的半导体器件
公开(公告)号：US07205795B2
公开(公告)日：2007-04-17
申请号：US11092943
申请日：2005-03-30
申请人： Masaharu Mizuno , Kazuhiro Nakajima
发明人： Masaharu Mizuno , Kazuhiro Nakajima
IPC分类号： H03K19/20
CPC分类号： H03K19/173
摘要： A universal logic module includes: a first inverter outputting an inverted input signal to an output terminal through a first transfer gate, the inverted input signal having an inverted level of an input signal provided from a first input terminal; and a second inverter outputting an inverted logic signal to the output terminal through a second transfer gate, the inverted logic signal having an inverted level of a first logic signal. The first input terminal is connected to one of a power supply line and a ground line. An input of the first transfer gate is directly connected to the other of the power supply line and the ground line. The first and the second transfer gates are complementarily turned on/off according to a level of a second logic signal. A result of a logical operation between the first and the second logic signals is outputted from the output terminal.
摘要翻译：通用逻辑模块包括：第一反相器，通过第一传输门将反相输入信号输出到输出端，反相输入信号具有从第一输入端提供的输入信号的反相电平; 以及第二反相器，通过第二传输门将输出反相逻辑信号输出到输出端，反相逻辑信号具有第一逻辑信号的反相电平。第一输入端子连接到电源线和接地线之一。第一传输门的输入直接连接到电源线和接地线中的另一个。根据第二逻辑信号的电平，第一和第二传输门互补地导通/截止。从输出端子输出第一和第二逻辑信号之间的逻辑运算的结果。

12. 发明授权

US06924671B2 General-purpose logic module and cell using the same 有权
标题翻译：通用逻辑模块和电池使用相同
公开(公告)号：US06924671B2
公开(公告)日：2005-08-02
申请号：US10418039
申请日：2003-04-18
申请人： Masaharu Mizuno
发明人： Masaharu Mizuno
IPC分类号： H03K19/173 , H03K19/094
CPC分类号： H03K19/1737
摘要： A general-purpose logic module is composed of: a first inverter 10 in which an input terminal is connected to a first node T1; a second node T2 connected to an output terminal of the first inverter; a second inverter 11 in which an input terminal is connected to a third node T3; a sixth node T6 connected to an output terminal of the second inverter; a third inverter 12 in which an input terminal is connected to a fourth node T4; a first transfer gate 20 in which an input terminal is connected to the output terminal of the first inverter, a first control input terminal is connected to the fourth node T4, and a second control input terminal is connected to an output terminal of the third inverter; a second transfer gate 21 in which an input terminal is connected to the output terminal of the second inverter, a first control input terminal is connected to the output terminal of the third inverter, and a second control input terminal is connected to the fourth node T4; and a fifth node T5 connected to an output terminal of the first transfer gate and an output terminal of the second transfer gate. Accordingly, it is possible to provide a general-purpose logic module in which a switch can be carried out at a high speed, and a cell using the same.
摘要翻译：通用逻辑模块包括：第一反相器10，其中输入端子连接到第一节点T1; 连接到第一反相器的输出端的第二节点T 2; 第二反相器11，其中输入端子连接到第三节点T 3; 连接到第二反相器的输出端的第六节点T 6; 第三反相器12，其中输入端子连接到第四节点T 4; 第一传输门20，其中输入端连接到第一反相器的输出端，第一控制输入端连接到第四节点T 4，第二控制输入端连接到第三反相器的输出端变频器; 第二传输门21，其中输入端子连接到第二反相器的输出端，第一控制输入端连接到第三反相器的输出端，第二控制输入端连接到第四节点T 4; 以及连接到第一传输门的输出端和第二传输门的输出端的第五节点T 5。因此，可以提供其中可以高速执行开关的通用逻辑模块和使用该通用逻辑模块的单元。

13. 发明授权

US5340522A Process for producing polyvinyl alcohol multifilament yarn 失效
标题翻译：生产聚乙烯醇复丝纱的方法
公开(公告)号：US5340522A
公开(公告)日：1994-08-23
申请号：US142924
申请日：1993-10-29
申请人： Atsushi Taniguchi , Masaharu Mizuno , Mitsuo Suzuki
发明人： Atsushi Taniguchi , Masaharu Mizuno , Mitsuo Suzuki
IPC分类号： B60C9/00 , D01F6/18 , D01F6/34 , D01F11/06 , D01F6/14 , C08F8/00 , C08F16/06 , C08G63/48
CPC分类号： B60C9/0042 , D01F11/06 , D01F6/18 , D01F6/34 , Y10S57/902
摘要： A multifilament yarn of polyvinyl alcohol having a degree of polymerization of at least 1500, the yarn having a tensile strength of at least 10 g/d and an index of hot water resistance of at least 50.
摘要翻译：聚合度至少为1500的聚乙烯醇的复丝纱线，拉伸强度为10g / d以上，耐热水性指数为50以上。

14. 发明授权

US4793131A Tire cord made of polyvinyl alcohol 失效
标题翻译：由聚乙烯醇制成的轮胎帘线
公开(公告)号：US4793131A
公开(公告)日：1988-12-27
申请号：US26794
申请日：1987-02-11
申请人： Masaharu Mizuno , Mituo Katoh
发明人： Masaharu Mizuno , Mituo Katoh
IPC分类号： B29D30/38 , B60C9/00 , B60C9/02 , B60C9/18 , D01F6/14 , D02G3/02 , D02G3/48
CPC分类号： D02G3/02 , B60C9/0042 , D02G3/48 , Y10S57/902
摘要： Tire cord having enough high tensile strength, high initial modulus, and high fatigue resistance required for radial tire and belted bias tire can be obtained from polyvinyl alcohol polymer. Said cord is constituted by multifilament yarns composed of a polyvinyl alcohol polymer having a degree of polymerization of at least 2000, having a tensile strength of 15 g/d or more and an initial modulus of 250 g/d or more, and undergoing substantially no fusion between single filaments. It has cord properties of not less than 8.5 g/d in tensile strength, 0.5 to 2.2% in middle degree of elongation (MDE), and 0.2 to 2.0% in dry heat shrinkage factor (.DELTA.S).
摘要翻译： PCT No.PCT / JP86 / 00286 Sec。 371日期1987年2月11日 102（e）1987年2月11日PCT PCT。1986年6月10日PCT公布。公开号WO86 / 07393 日期：1986年12月18日。可以从聚乙烯醇聚合物获得具有足够高的拉伸强度，高初始模量和子午线轮胎和带式偏置轮胎所需的高抗疲劳性的轮胎帘线。所述帘线是由聚合度为2000以上，聚合度为15g / d以上，初始模量为250g / d以上的聚乙烯醇聚合物构成的复丝构成，单丝之间的融合。帘线性能的拉伸强度不低于8.5g / d，中等伸长率（MDE）为0.5〜2.2％，干热收缩率（DELTA S）为0.2〜2.0％。

15. 发明授权

US07161382B2 General-purpose logic cell, general-purpose logic cell array using the same, and ASIC using general-purpose logic cell array 有权
标题翻译：通用逻辑单元，使用相同的通用逻辑单元阵列，以及使用通用逻辑单元阵列的ASIC
公开(公告)号：US07161382B2
公开(公告)日：2007-01-09
申请号：US10438012
申请日：2003-05-15
申请人： Masaharu Mizuno , Tooru Fujii
发明人： Masaharu Mizuno , Tooru Fujii
IPC分类号： H03K19/177
CPC分类号： H03K19/1735
摘要： A general-purpose logic cell used in a general-purpose logic cell array for a logic circuit, includes a plurality of kinds of logic circuit elements, each of which has a plurality of terminals with no connection. The plurality of kinds of logic circuit elements includes a flip-flop and a first inverter set. In this case, each of first inverters of the first inverter set is possible to be connected with an input of the flip-flop in parallel or as one of a series connection of at least two of the first inverters. Also, each first inverter is possible to be connected with an output of the flip-flop in parallel or as one of a series connection of at least two of the first inverters.
摘要翻译：在用于逻辑电路的通用逻辑单元阵列中使用的通用逻辑单元包括多种逻辑电路元件，每个逻辑电路元件具有多个不具有连接的端子。多种逻辑电路元件包括触发器和第一反相器组。在这种情况下，第一反相器组的第一反相器中的每一个都可以与触发器的输入端并联连接或者与至少两个第一反相器的串联连接中的一个连接。此外，每个第一反相器可以并联地连接到触发器的输出或者作为至少两个第一反相器的串联连接之一。

16. 发明申请

US20060189041A1 Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign 有权
公开(公告)号：US20060189041A1
公开(公告)日：2006-08-24
申请号：US11385767
申请日：2006-03-22
申请人： Masaharu Mizuno , Naotaka Maeda
发明人： Masaharu Mizuno , Naotaka Maeda
IPC分类号： H01L23/58 , H01L21/82 , H01L29/10
CPC分类号： H01L27/118
摘要： An ASIC includes a function layer formed with plural universal logic cells, a common layer formed with conductive strips connected to the universal logic cells and common to other ASICs and a customized layer having at least two metallization layers assigned to conductive strips extending in certain directions parallel to one another and other conductive strips extending in perpendicular directions to the certain directions, respectively, and an inter-layered insulating layer formed with conductive plugs selectively connected between the conductive strips and the other conductive strips, wherein the conductive strips have respective values of length such that the conductive plugs are located on both ends thereof, whereby the conductive strips, other conductive strips and the conductive plugs form plural signal paths reduced in total contact resistance and parasitic capacitance.

17. 发明授权

US06853019B2 Semiconductor device and manufacturing method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US06853019B2
公开(公告)日：2005-02-08
申请号：US10437391
申请日：2003-05-14
申请人： Masaharu Mizuno , Shigeo Noda
发明人： Masaharu Mizuno , Shigeo Noda
IPC分类号： H01L21/822 , H01L21/82 , H01L27/02 , H01L27/04 , H01L27/118 , H03K19/173 , H03K19/177 , H10L27/10
CPC分类号： H01L27/0207 , H01L27/11807 , H01L27/11898 , H03K19/17728 , H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A semiconductor device includes a plurality of logic cells formed on a semiconductor substrate, wherein each of the plurality of logic cells has a circuit for a function block of a logic circuit; and a wiring layer which connects the plurality of logic cells to form the logic circuit function blocks and thereby the logic circuit. The wiring layer includes a power supply wiring line pattern formed in a region corresponding to each of the plurality of logic cells; a ground wiring line pattern formed in the region; and a plurality of terminal patterns formed in the region. Each of the plurality of terminal patterns is connected with the circuit of the logic cell, and the plurality of terminal patterns are arranged adjacent to at least one of the power supply wiring line pattern and the ground wiring line pattern.
摘要翻译：半导体器件包括形成在半导体衬底上的多个逻辑单元，其中多个逻辑单元中的每一个具有用于逻辑电路的功能块的电路; 以及连接多个逻辑单元以形成逻辑电路功能块并由此连接逻辑电路的布线层。布线层包括形成在与多个逻辑单元中的每一个对应的区域中的电源布线图案; 在该区域中形成的接地布线图案; 以及形成在该区域中的多个端子图案。多个端子图案中的每一个与逻辑单元的电路连接，并且多个端子图案被布置为与电源布线图案和接地布线图案中的至少一个相邻。

18. 发明授权

US06674307B2 General-purpose logic module and cell using the same 有权
标题翻译：通用逻辑模块和单元使用相同
公开(公告)号：US06674307B2
公开(公告)日：2004-01-06
申请号：US09978721
申请日：2001-10-18
申请人： Masaharu Mizuno
发明人： Masaharu Mizuno
IPC分类号： H03K19094
CPC分类号： H03K19/1737
摘要： A general-purpose logic module is composed of: a first inverter 10 in which an input terminal is connected to a first node T1; a second node T2 connected to an output terminal of the first inverter; a second inverter 11 in which an input terminal is connected to a third node T3; a sixth node T6 connected to an output terminal of the second inverter; a third inverter 12 in which an input terminal is connected to a fourth node T4; a first transfer gate 20 in which an input terminal is connected to the output terminal of the first inverter, a first control input terminal is connected to the fourth node T4, and a second control input terminal is connected to an output terminal of the third inverter; a second transfer gate 21 in which an input terminal is connected to the output terminal of the second inverter, a first control input terminal is connected to the output terminal of the third inverter, and a second control input terminal is connected to the fourth node T4; and a fifth node T5 connected to an output terminal of the first transfer gate and an output terminal of the second transfer gate. Accordingly, it is possible to provide a general-purpose logic module in which a switch can be carried out at a high speed, and a cell using the same.
摘要翻译：通用逻辑模块包括：第一反相器10，其中输入端子连接到第一节点T1; 连接到第一反相器的输出端的第二节点T2; 第二反相器11，其中输入端子连接到第三节点T3; 连接到第二反相器的输出端的第六节点T6; 第三反相器12，其中输入端子连接到第四节点T4; 第一传输门20，其中输入端连接到第一反相器的输出端，第一控制输入端连接到第四节点T4，第二控制输入端连接到第三反相器的输出端 ; 第二传输门21，其中输入端连接到第二反相器的输出端，第一控制输入端连接到第三反相器的输出端，第二控制输入端与第四结点T4连接 ; 以及连接到第一传输门的输出端和第二传输门的输出端的第五节点T5。因此，可以提供其中可以高速执行开关的通用逻辑模块和使用该通用逻辑模块的单元。

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