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11. 发明授权

US07037777B2 Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding use of the etching mask 失效
标题翻译：在微观结构上制造蚀刻掩模的方法，特别是具有沟槽电容器的半导体结构以及蚀刻掩模的相应应用
公开(公告)号：US07037777B2
公开(公告)日：2006-05-02
申请号：US10801781
申请日：2004-03-16
申请人： Hans-Peter Moll , Momtchil Stavrev , Mirko Vogt , Stephan Wege
发明人： Hans-Peter Moll , Momtchil Stavrev , Mirko Vogt , Stephan Wege
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L21/3081 , H01L27/10867
摘要： Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching mask which allow for extremely thin photoresist layers to be employed.
摘要翻译：用于在微观结构上制造蚀刻掩模的方法，特别是具有沟槽电容器的半导体结构以及允许使用极薄的光致抗蚀剂层的蚀刻掩模的相应用途。

12. 发明申请

US20050245042A1 Fabrication method for a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US20050245042A1
公开(公告)日：2005-11-03
申请号：US11099962
申请日：2005-04-06
申请人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchil Stavrev , Stephan Wege
发明人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchil Stavrev , Stephan Wege
IPC分类号： H01L21/3065 , H01L21/762 , H01L21/8234 , H01L21/8242
CPC分类号： H01L21/76232
摘要： The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
摘要翻译：本发明提供一种半导体结构的制造方法，其具有提供半导体衬底（1）的步骤。在半导体衬底（1）上提供和图案化氮化硅层（3）作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽（5）; 在所得结构上保形地沉积由氧化硅制成的衬垫层（10），留下在沟槽（5）中深入的间隙（SP）; 执行V等离子体蚀刻步骤，用于在沟槽（5）中形成线层（10）的V轮廓; 其中所述衬垫层（10）被拉回到所述氮化硅层（3）的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2，在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例（V）在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。

13. 发明申请

US20050202626A1 Method for fabricating a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US20050202626A1
公开(公告)日：2005-09-15
申请号：US11071532
申请日：2005-03-04
申请人： Mihel Seitz , Stephan Wege
发明人： Mihel Seitz , Stephan Wege
IPC分类号： H01L21/308 , H01L21/31 , H01L21/3205 , H01L21/4763 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/108
CPC分类号： H01L29/66181 , H01L27/1087
摘要： The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate (1) made of silicon with a first hard mask layer (10; 10′) made of silicon oxide and an overlying second hard mask layer (15; 15′) made of silicon; providing a masking layer (30; 30′) made of silicon oxide above and laterally with respect to the second hard mask layer (15; 15′) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (1); providing a photoresist mask (25) above the masking layer (30; 30′) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (1); opening the masking layer (30; 30′) in a first plasma process using the photoresist mask (25), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer (10; 10′) and second hard mask layer (15; 15′) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate (1) in a fourth plasma process using the opened first hard mask layer (10; 10′); the edge region (RB) not being covered by the shielding device (AR) in the second to fourth plasma processes.
摘要翻译：本发明提供一种半导体结构的制造方法，其特征在于，具有以下步骤：提供由硅制成的半导体衬底（1），所述半导体衬底（1）由氧化硅制成的第一硬掩模层（10; 10'）和覆盖的第二硬掩模层 15; 15'）由硅制成; 在半导体衬底（1）的未覆盖边缘区域（RB）上方提供相对于由硅制成的第二硬掩模层（15; 15'）上方和侧面的由氧化硅制成的掩模层（30; 30'）， ; 在所述掩模层（30; 30'）上方设置与所述半导体衬底（1）中形成的沟槽（DT）对应的开口的光致抗蚀剂掩模（25）; 在使用光致抗蚀剂掩模（25）的第一等离子体工艺中打开掩模层（30; 30'），边缘区域（RB）被屏蔽装置（AR）覆盖; 在第二和第三等离子体工艺中打开第一硬掩模层（10; 10'）和第二硬掩模层（15; 15'）; 以及使用所述打开的第一硬掩模层（10; 10'）在第四等离子体工艺中在所述半导体衬底（1）中形成所述沟槽（DT）。在第二至第四等离子体处理中边缘区域（RB）不被屏蔽装置（AR）覆盖。

14. 发明授权

US10971340B2 Gas injector for reaction regions 有权
公开(公告)号：US10971340B2
公开(公告)日：2021-04-06
申请号：US16098886
申请日：2017-05-12
申请人： Stephan Wege
发明人： Stephan Wege
IPC分类号： H01J37/32 , H01J37/075 , H01J37/34 , C23C16/455
摘要： The invention relates to a gas injector (10) for supplying gas or a gas mixture to a reaction region (16). The gas injector (10) contains a main part (12) with a gas channel (14). Furthermore, a gas feed (30) is provided for the gas channels (14). The gas or the gas mixture reaches the reaction region (16) from the gas channel (14) via a first opening (26) or a first group (54) of openings (26) in the main part. The main part (12) is equipped with a second opening (27) or a second group (56) of openings (27) via which the gas of the gas mixture likewise reaches the reaction region (16) from the gas channel (14). Each of the openings (26, 27) or the groups (54, 56) of openings (26, 27) is paired with a respective separate gas feed (30, 40) in the main part (12) on the gas channel (14).

15. 发明授权

US07879395B2 Method of preparing a coating solution and a corresponding use of the coating solution for coating a substrate 有权
标题翻译：制备涂布溶液的方法以及用于涂布基材的涂布溶液的相应用途
公开(公告)号：US07879395B2
公开(公告)日：2011-02-01
申请号：US11582239
申请日：2006-10-17
申请人： Andreas Klipp , Stephan Wege , Tobias Mayer-Uhma , Cornelia Klein , Alexander Michaelis , Falko Schlenkrich
发明人： Andreas Klipp , Stephan Wege , Tobias Mayer-Uhma , Cornelia Klein , Alexander Michaelis , Falko Schlenkrich
IPC分类号： B05D3/12
CPC分类号： H01L21/02282 , H01L21/02178 , H01L21/02189 , H01L21/316
摘要： A method of preparing a coating solution, comprising the steps of providing a first solution comprising a lower alcohol; a polyethylene glycol; a complexing agent; and water; providing a second solution comprising a higher alcohol; and at least one metal alkoxide, wherein the metal in said at least one metal alkoxide is selected from the group consisting of zirconium, aluminium, titanium, tantalum and yttrium; forming a sol-gel solution by mixing said first and second solutions and thereby hydrolyzing said at least one metal alkoxide to a metal oxide and an alcohol; forming a concentrated solution by removing said lower alcohol and the alcohol resulting from the hydrolysis of said at least one metal alkoxide; and forming a coating solution by adding a medium alcohol to said concentrated solution.
摘要翻译：一种制备涂布溶液的方法，包括以下步骤：提供包含低级醇的第一溶液; 聚乙二醇; 络合剂和水; 提供包含高级醇的第二溶液; 和至少一种金属醇盐，其中所述至少一种金属醇盐中的金属选自锆，铝，钛，钽和钇; 通过混合所述第一和第二溶液形成溶胶 - 凝胶溶液，从而将所述至少一种金属醇盐水解成金属氧化物和醇; 通过除去由所述至少一种金属醇盐的水解产生的所述低级醇和醇形成浓缩溶液; 以及通过向所述浓缩溶液中加入中等醇形成涂布溶液。

16. 发明授权

US07544270B2 Apparatus for processing a substrate 失效
标题翻译：用于处理衬底的装置
公开(公告)号：US07544270B2
公开(公告)日：2009-06-09
申请号：US11273244
申请日：2005-11-14
申请人： Stephan Wege , Roger-Michael Wolf
发明人： Stephan Wege , Roger-Michael Wolf
IPC分类号： H01L21/00 , C23C16/00
CPC分类号： H01L21/67069 , H01J37/32623 , H01J37/32642
摘要： An apparatus includes a plasma process chamber and a support element capable of supporting a substrate inside the plasma process chamber. At least one plasma control element is placed adjacent to a peripheral portion of the support element such that the plasma control element is capable of influencing a plasma inside the plasma process chamber if an electric field is applied thereto. At least one voltage generator is connected to the plasma control element. The plasma control element is movable inside the process chamber such that it can be set to any of at least two different positions.
摘要翻译：一种装置包括等离子体处理室和能够支撑等离子体处理室内的基板的支撑元件。至少一个等离子体控制元件被放置成与支撑元件的周边部分相邻，使得等离子体控制元件能够影响等离子体处理室内的等离子体，如果对其施加电场。至少一个电压发生器连接到等离子体控制元件。等离子体控制元件可以在处理室内移动，使得其可以被设置为至少两个不同位置中的任何一个。

17. 发明申请

US20090102023A1 Method for Manufacturing a Structure, Semiconductor Device and Structure on a Substrate 审中-公开
标题翻译：在基板上制造结构，半导体器件和结构的方法
公开(公告)号：US20090102023A1
公开(公告)日：2009-04-23
申请号：US11875140
申请日：2007-10-19
申请人： Stephan Wege , Chirstoph Noelscher , Alfred Kersch , Hocine Boubekeur , Christoph Ludwig
发明人： Stephan Wege , Chirstoph Noelscher , Alfred Kersch , Hocine Boubekeur , Christoph Ludwig
IPC分类号： H01L29/06 , H01L21/31 , H01L21/311
CPC分类号： H01L21/0337 , B81C1/00111 , H01L21/0338
摘要： One possible embodiment is a method for manufacturing a structure on a substrate which can be used in the manufacturing of a semiconductor device, including the steps of: forming a first structure on the substrate having at least one sidewall, forming at least one layer as a second structure selectively on the at least one sidewall of the first structure by an epitaxial technique, electroplating, selective silicon dioxide deposition, selective low pressure CVD or an atomic layer deposition technique. Furthermore semiconductor devices, uses of equipment and structures are covered.
摘要翻译：一个可能的实施例是用于制造可用于制造半导体器件的衬底上的结构的方法，包括以下步骤：在具有至少一个侧壁的衬底上形成第一结构，形成至少一层作为第二结构通过外延技术，电镀，选择性二氧化硅沉积，选择性低压CVD或原子层沉积技术选择性地在第一结构的至少一个侧壁上。此外，还涵盖了半导体器件，设备和结构的使用。

18. 发明申请

US20050196952A1 Method for production of a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US20050196952A1
公开(公告)日：2005-09-08
申请号：US11065342
申请日：2005-02-25
申请人： Oliver Genz , Markus Kirchhoff , Stefan Machill , Alexander Reb , Barbara Schmidt , Momtchil Stavrev , Maik Stegeman , Stephan Wege
发明人： Oliver Genz , Markus Kirchhoff , Stefan Machill , Alexander Reb , Barbara Schmidt , Momtchil Stavrev , Maik Stegeman , Stephan Wege
IPC分类号： H01L21/027 , H01L21/033 , H01L21/308 , H01L21/311 , H01L21/4763 , H01L21/768 , H01L21/8234 , H01L21/8244
CPC分类号： H01L21/76811 , H01L21/0276 , H01L21/0332 , H01L21/3081 , H01L21/31144
摘要： A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.
摘要翻译：一种制造半导体结构的方法，包括制备半导体衬底，并在所述半导体衬底的表面上产生下部第一，中间第二和上部第三掩模层。该方法还包括在上部第三掩蔽层中形成至少一个第一窗口，使用用于传送第一窗口的第一窗口构造中间第二掩蔽层，使用用于传送第一窗口的第一窗口构造下部第一掩蔽层，以及扩大第一个窗口形成第二个窗口。该方法还包括：使用第二窗口重建中间第二掩蔽层，使用结构化的下部第三掩蔽层，使用第二窗口重构下部第一掩蔽层，并重构半导体衬底，构建半导体衬底; 使用重组的下三层掩蔽层。

19. 发明申请

US20050148193A1 Photolithographic method for forming a structure in a semiconductor substrate 审中-公开
标题翻译：用于在半导体衬底中形成结构的光刻方法
公开(公告)号：US20050148193A1
公开(公告)日：2005-07-07
申请号：US10496102
申请日：2002-11-14
申请人： Markus Kirchhoff , Mirko Vogt , Stephan Wege , Frank Katzwinkel
发明人： Markus Kirchhoff , Mirko Vogt , Stephan Wege , Frank Katzwinkel
IPC分类号： G03F7/09 , H01L21/027 , H01L21/033 , H01L21/308 , H01L21/31 , H01L21/311 , H01L21/312 , H01L21/3213 , H01L21/762 , H01L21/8242
CPC分类号： H01L21/3081 , H01L21/02115 , H01L21/02274 , H01L21/312
摘要： To form a pattern in a semiconductor substrate, a buffer layer, which is formed as a carbon layer, is produced between a photoresist layer and an antireflective layer, which is formed on the substrate. The pattern is produced in the photoresist layer by means of a lithography step, and then it is transferred to the layers arranged below in a subsequent step.
摘要翻译：为了在半导体衬底中形成图案，在形成在衬底上的光致抗蚀剂层和抗反射层之间产生形成为碳层的缓冲层。通过光刻步骤在光致抗蚀剂层中产生图案，然后将其转移到随后的步骤中布置在下面的层中。

20. 发明授权

US06596625B2 Method and device for producing a metal/metal contact in a multilayer metallization of an integrated circuit 有权
公开(公告)号：US06596625B2
公开(公告)日：2003-07-22
申请号：US09932899
申请日：2001-08-20
申请人： Martin Schneegans , Stephan Wege
发明人： Martin Schneegans , Stephan Wege
IPC分类号： H01L214763
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76802 , H01L21/76814
摘要： Metal/metal contacts are formed as part of a multilayer metallization in an integrated circuit on a semiconductor wafer. The application of an insulation layer on a metal level is followed by a lithography step using a photoresist mask to define contact holes on the insulation layer, followed by anisotropic etching of the insulation layer in order to produce the contact holes. Then, a chemical dry etch that removes the photoresist mask and a chemical-physical dry etch that removes organic impurities which accumulate during the chemical dry etch are successively carried out in a vacuum. Subsequently, a metal deposition step is carried out in order to fill the contact holes.

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