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11. 发明授权

US6087706A Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls 失效
标题翻译：紧凑的晶体管结构，具有相邻的沟槽隔离和源极/漏极区域，垂直注入沟槽壁
公开(公告)号：US6087706A
公开(公告)日：2000-07-11
申请号：US56834
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/265 , H01L21/762 , H01L21/8234 , H01L29/417 , H01L29/78 , H01L29/00 , H01L29/94
CPC分类号： H01L21/26586 , H01L21/76224 , H01L21/823418 , H01L21/823443 , H01L21/823475 , H01L21/823481 , H01L29/41766 , H01L29/66636 , H01L29/7833
摘要： A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate electrode is formed over a portion of the active area and LDD regions formed that are self-aligned to both the gate electrode and the trench side-walls. A dielectric spacer is formed adjacent the gate electrode and extending to the trench side-walls. In this manner, the spacers essentially cover the LDD regions. Source and drain regions are formed that are adjacent the trench side-walls wherein the spacer serves to protect at least a portion of the LDD regions to maintain a spacing of the S/D regions from the gate electrode edge. In this manner an advantageously lowered E.sub.M provided by LDD regions is maintained. In some embodiments of the present invention, S/D regions are formed by implantation through the trench side-walls.
摘要翻译：描述了一种形成在由浅沟槽隔离区域的侧壁限定的有源区域内的晶体管的半导体集成电路及其制造方法。在有源区域的一部分上形成栅电极，形成与栅极电极和沟槽侧壁自对准的LDD区域。形成在栅电极附近并延伸到沟槽侧壁的电介质垫片。以这种方式，间隔件基本上覆盖LDD区域。形成与沟槽侧壁相邻的源极区和漏极区，其中间隔物用于保护LDD区的至少一部分以保持S / D区与栅电极边缘的间隔。以这种方式，维持由LDD区域提供的有利的降低的EM。在本发明的一些实施例中，通过在沟槽侧壁上注入形成S / D区域。

12. 发明授权

US6040607A Self aligned method for differential oxidation rate at shallow trench isolation edge 失效
标题翻译：浅沟槽隔离边缘微分氧化率自对准方法
公开(公告)号：US6040607A
公开(公告)日：2000-03-21
申请号：US928607
申请日：1998-02-23
申请人： Derick J. Wristers , H. Jim Fulford , Mark I. Gardner
发明人： Derick J. Wristers , H. Jim Fulford , Mark I. Gardner
IPC分类号： H01L21/762 , H01L27/02 , H01L29/68
CPC分类号： H01L21/76237
摘要： A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the proximal portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.
摘要翻译：提供其中在半导体衬底中形成至少一个隔离结构的半导体工艺。氧离子种类被引入半导体衬底的靠近隔离结构的部分，优选通过使用离子注入到倾斜或倾斜的衬底中。然后在半导体衬底的上表面上形成栅介质层。在半导体衬底的近端部分存在含氧物质增加了近端部分相对于远离隔离结构的衬底部分的氧化速率的氧化速率。以这种方式，在半导体衬底的近端部分上的栅极电介质的第一厚度大于半导体衬底的剩余部分上的栅极氧化物层的第二厚度。与隔离沟槽的不连续性相邻的增加的氧化物厚度减小了跨过氧化物的电场。

13. 发明授权

US5994175A High performance MOSFET with low resistance design 失效
标题翻译：具有低电阻设计的高性能MOSFET
公开(公告)号：US5994175A
公开(公告)日：1999-11-30
申请号：US924781
申请日：1997-09-05
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814
摘要： A manufacturing process in which semiconductor transistors are fabricated using a fluorine or nitrogen implant into the n-channel regions and an amorphization implant to beneficially limit the spreading of the source/drain impurity distributions thereby decreasing the junction depth and increasing the sheet resistance of the source/drain regions. Broadly speaking, a gate dielectric layer is formed on a semiconductor substrate. First and second conductive gate structures are then formed on an upper surface of the gate dielectric layer. The first conductive gate is positioned over the p-well region while the second conductive gate is positioned over the n-well region. An n-channel mask is then formed on the substrate and a first impurity distribution is introduced into the p-well regions. The first impurity distribution preferably includes a species of fluorine or nitrogen. A n-type impurity distribution is then introduced into the p-well regions of the semiconductor substrate. A p-channel mask is then formed on the semiconductor substrate. After the p-channel mask is formed, a p-type impurity distribution such as boron is introduced into the n-well regions and into the second conductive gate structure. An electrically neutral impurity is then introduced into the semiconductor substrate to amorphize the semiconductor substrate to limit the subsequent redistribution of source/drain impurity distributions thereby resulting in the formation of shallow junctions. Thereafter, spacer structures are formed on sidewalls of the first and second conductive gate structures, and forming the spacer structures, n+ and p+ source/drain impurity distributions are introduced into the p and n well regions of the semiconductor substrate respectively.
摘要翻译：使用氟或氮注入到n沟道区域中制造半导体晶体管的制造工艺和非晶化注入，以有利地限制源极/漏极杂质分布的扩展，从而减小结深度并增加源极的薄层电阻 /漏区。广义地说，在半导体衬底上形成栅介质层。然后在栅介质层的上表面上形成第一和第二导电栅极结构。第一导电栅极位于p阱区上方，而第二导电栅极位于n阱区上方。然后在衬底上形成n沟道掩模，并将第一杂质分布引入p阱区。第一杂质分布优选包括一种氟或氮的种类。然后将n型杂质分布引入半导体衬底的p阱区。然后在半导体衬底上形成p沟道掩模。在形成p沟道掩模之后，诸如硼的p型杂质分布被引入n阱区并进入第二导电栅极结构。然后将电中性杂质引入半导体衬底中以使半导体衬底非晶化，以限制随后的源/漏杂质分布的再分配，从而导致形成浅结。此后，在第一和第二导电栅极结构的侧壁上形成间隔结构，并且形成间隔结构，将n +和p +源极/漏极杂质分布分别引入半导体衬底的p阱区和n阱区。

14. 发明授权

US5885887A Method of making an igfet with selectively doped multilevel polysilicon gate 失效
标题翻译：用选择性掺杂多电平多晶硅栅极制造igfet的方法
公开(公告)号：US5885887A
公开(公告)日：1999-03-23
申请号：US847752
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/423 , H01L21/38
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/823842 , H01L29/42376
摘要： A method of making an IGFET with a selectively doped multilevel polysilicon gate that includes upper and lower polysilicon gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a a lower polysilicon layer on the gate insulator, forming a first masking layer over the lower polysilicon layer, etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms the lower polysilicon gate level over the active region, removing the first masking layer, forming the upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate, diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level, and forming a source and drain in the active region. Advantageously, the lower polysilicon gate level has both an accurately defined length to provide the desired channel length and a well-controlled doping concentration to provide the desired threshold voltage.
摘要翻译：公开了一种制造具有选择性掺杂多电平多晶硅栅极的IGFET的方法，其包括上和下多晶硅栅极电平。该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上形成下部多晶硅层，在下部多晶硅层上形成第一掩蔽层，通过下部多晶硅层的开口蚀刻下部多晶硅层所述第一掩模层使用所述第一掩模层作为用于在所述有源区上形成所述下多晶硅栅极电平的所述下多晶硅层的一部分的蚀刻掩模，去除所述第一掩模层，在所述下多晶硅栅极上形成所述上多晶硅栅极电平在去除第一掩模层之后，将掺杂剂引入上多晶硅栅极级，而不将掺杂剂引入衬底中，将掺杂剂从上多晶硅栅极级扩散到下多晶硅栅极电平，并在活性层中形成源极和漏极地区。有利地，下多晶硅栅极电平具有精确限定的长度以提供期望的沟道长度和良好控制的掺杂浓度以提供期望的阈值电压。

15. 发明授权

US5877050A Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals 失效
标题翻译：使用两个管退火和两个快速热退火来制造N沟道和P沟道器件的方法
公开(公告)号：US5877050A
公开(公告)日：1999-03-02
申请号：US711956
申请日：1996-09-03
申请人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford, Jr.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814
摘要： A method of making N-channel and P-channel IGFETs is disclosed. The method includes, in sequence, the steps of partially doping a first source and a first drain in a first active region of a semiconductor substrate, applying a first tube anneal while a second active region of the semiconductor substrate is devoid of source/drain doping, partially doping a second source and a second drain in the second active region, applying a second tube anneal, fully doping the first source and the first drain, applying a first rapid thermal anneal, fully doping the second source and the second drain, and applying a second rapid thermal anneal. Advantageously, the first and second tube anneals provide control over the channel junction locations, and the first and second rapid thermal anneals provide rapid drive-in for subsequent source/drain doping spaced from the channel junctions.
摘要翻译：公开了制造N沟道和P沟道IGFET的方法。该方法依次包括在半导体衬底的第一有源区域中部分地掺杂第一源极和第一漏极的步骤，施加第一管退火，而半导体衬底的第二有源区域没有源极/漏极掺杂在第二有源区中部分地掺杂第二源极和第二漏极，施加第二管退火，完全掺杂第一源极和第一漏极，施加第一快速热退火，完全掺杂第二源极和第二漏极，以及应用第二快速热退火。有利地，第一和第二管退火提供对通道结位置的控制，并且第一和第二快速热退火为与通道结隔开的后续源极/漏极掺杂提供快速驱动。

16. 发明授权

US5869879A CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions 失效
公开(公告)号：US5869879A
公开(公告)日：1999-02-09
申请号：US761399
申请日：1996-12-06
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L29/78 , H01L29/00
CPC分类号： H01L29/7833 , H01L21/823814 , Y10S257/90
摘要： An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, an MDD area and a heavy concentration source/drain area. Conversely, the PMOS transistor include an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provide lower source/drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.

17. 发明授权

US5811222A Method of selectively exposing a material using a photosensitive layer and multiple image patterns 失效
标题翻译：使用感光层和多个图像图案选择性地曝光材料的方法
公开(公告)号：US5811222A
公开(公告)日：1998-09-22
申请号：US668688
申请日：1996-06-24
申请人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford, Jr.
IPC分类号： H01L29/78 , G03F7/20 , H01L21/02 , H01L21/027 , H01L21/033
CPC分类号： G03F7/70466 , G03F7/2022 , G03F7/70475 , H01L21/0334
摘要： A method of selectively exposing a material over a substrate is disclosed. The method includes forming a material over a semiconductor substrate, forming a photosensitive layer over the material, projecting a first image pattern onto the photosensitive layer that defines a first boundary for the material, projecting a second image pattern onto the photosensitive layer after projecting the first image pattern such that the second image pattern partially overlaps the first image pattern and defines a second boundary for the material, and removing portions of the photosensitive layer corresponding to the first and second image patterns. Preferably, the first and second image patterns are essentially identical to and laterally shifted with respect to one another. In this manner, the photosensitive layer selectively exposes the material adjacent to the first and second boundaries while covering the material between the first and second boundaries, and the distance between the first and second boundaries decreases as the overlap between the first and second image patterns decreases. Advantageously, the first and second boundaries can be closer than the minimum resolution of the photolithographic system used to pattern the photosensitive layer.
摘要翻译：公开了一种在衬底上选择性地暴露材料的方法。该方法包括在半导体衬底上形成材料，在材料上形成感光层，将第一图案图案投射到限定材料的第一边界的光敏层上，将第一图像图案投射到感光层上，图像图案，使得第二图像图案部分地与第一图像图案重叠并且限定材料的第二边界，以及去除与第一和第二图像图案相对应的感光层的部分。优选地，第一和第二图像图案基本上彼此相同并且相对于彼此横向移位。以这种方式，感光层选择性地暴露与第一和第二边界相邻的材料，同时覆盖第一和第二边界之间的材料，并且第一和第二边界之间的距离随着第一和第二图像图案之间的重叠减小而减小。有利地，第一和第二边界可以比用于图案感光层的光刻系统的最小分辨率更接近。

18. 发明授权

US5648286A Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region 失效
标题翻译：制造具有轻掺杂漏极区域，重掺杂源极和漏极区域以及超重掺杂源极区域的不对称晶体管的方法
公开(公告)号：US5648286A
公开(公告)日：1997-07-15
申请号：US711383
申请日：1996-09-03
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66659 , H01L29/7835
摘要： An asymmetrical IGFET including a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped source region outside the first spacer into an ultra-heavily doped source region without doping a portion of the heavily doped source region beneath the first spacer, and to convert a portion of the lightly doped drain region outside the second spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the second spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.
摘要翻译：公开了一种包括轻掺杂漏极区域，重掺杂源极和漏极区域以及超重掺杂源极区域的非对称IGFET。优选地，轻掺杂漏极区域和重掺杂源极区域提供通道结。制造IGFET的方法包括提供半导体衬底，在衬底上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂的源极和漏极区域注入到衬底中，施加第二离子注入以将轻掺杂源区域分成重掺杂源区，而不掺杂轻掺杂漏极区，分别与第一和第二侧壁相邻形成第一和第二间隔，并施加第三离子注入以将重掺杂源区的一部分转换到外部所述第一间隔物进入超重掺杂源区，而不掺杂所述第一间隔物下方的重掺杂源区的一部分，以及将所述第二间隔区外部的所述轻掺杂漏极区的一部分转换为重掺杂漏极区，而不掺杂第二间隔物下方的轻掺杂漏极区的部分。有利地，IGFET具有低的源极 - 漏极串联电阻并且降低热载流子效应。

19. 发明授权

US06372588B2 Method of making an IGFET using solid phase diffusion to dope the gate, source and drain 失效
标题翻译：使用固相扩散制造IGFET以掺杂栅极，源极和漏极的方法
公开(公告)号：US06372588B2
公开(公告)日：2002-04-16
申请号：US08837523
申请日：1997-04-21
申请人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
发明人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L21/2256 , H01L21/32155 , H01L29/665
摘要： A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device region, forming a heavily doped diffusion source layer over the insulating layer, and driving a dopant from the diffusion source layer through the insulating layer into the gate and the device region by solid phase diffusion, thereby heavily doping the gate and forming a heavily doped source and drain in the device region. Preferably, the gate and diffusion source layer are polysilicon, the gate insulator and insulating layer are silicon dioxide, the dopant is boron or boron species, and the dopant provides essentially all P-type doping for the gate, source and drain, thereby providing shallow channel junctions and reducing or eliminating boron penetration from the gate into the substrate.
摘要翻译：公开了使用固相扩散制造IGFET的方法。该方法包括在半导体衬底中提供器件区域，在器件区域上形成栅极绝缘体，在栅极绝缘体上形成栅极，在栅极和器件区域上形成绝缘层，在其上形成重掺杂扩散源层绝缘层，并且通过固相扩散将掺杂剂从扩散源层驱动通过绝缘层进入栅极和器件区域，从而大量掺杂栅极并在器件区域中形成重掺杂的源极和漏极。优选地，栅极和扩散源层是多晶硅，栅绝缘体和绝缘层是二氧化硅，掺杂剂是硼或硼物质，并且掺杂剂为栅极，源极和漏极提供基本上所有的P型掺杂，从而提供浅通道结并且减少或消除从孔进入衬底的硼渗透。

20. 发明授权

US06259142B1 Multiple split gate semiconductor device and fabrication method 失效
标题翻译：多分裂栅极半导体器件及其制造方法
公开(公告)号：US06259142B1
公开(公告)日：2001-07-10
申请号：US09056837
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L2976
CPC分类号： H01L29/66484 , H01L29/7831
摘要： A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another by means of a gate insulating layer that is formed adjacent the side-walls of each firs gate electrode. Source and drain regions are formed adjacent the ends of the multiple split gate to define a channel region.
摘要翻译：具有多个分割栅极的半导体集成电路使用第一多晶硅层和第二多晶硅层形成，以在有源区内形成交替的第一和第二栅电极。交替的栅电极通过与每个第一栅电极的侧壁相邻形成的栅极绝缘层彼此电隔离。源极和漏极区域形成在多分裂栅极的端部附近以限定沟道区域。

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