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11. 发明授权

US5764564A Write-assisted memory cell and method of operating same 失效
标题翻译：写辅助存储单元及其操作方法
公开(公告)号：US5764564A
公开(公告)日：1998-06-09
申请号：US814248
申请日：1997-03-11
申请人： Scott O. Frake , Philip D. Costello
发明人： Scott O. Frake , Philip D. Costello
IPC分类号： G11C11/412 , G11C11/00
CPC分类号： G11C11/412
摘要： For a memory cell comprising a latch with cross-coupled inverters and an n-channel access transistor, the inverter that can contend with the access transistor is connected not between power and ground but between power and a transistor that disconnects the inverter from ground when the memory cell is being written. This allows transistors in the memory cell to be small and still function properly, without requiring that a port be provided for the complement of the data signal. The invention is important when there are several write ports to the memory cell and the addressing overhead is significant.
摘要翻译：对于包括具有交叉耦合的反相器的锁存器和n沟道存取晶体管的存储器单元，可以与存取晶体管相抗衡的反相器不是连接在电源和地之间，而是连接在功率与晶体管之间，当晶体管与地内存单元正在写入。这允许存储器单元中的晶体管小并且仍然正常工作，而不需要为数据信号的补码提供端口。当存在存储单元的多个写入端口并且寻址开销很大时，本发明是重要的。

12. 发明授权

US07187709B1 High speed configurable transceiver architecture 有权
标题翻译：高速可配置收发器架构
公开(公告)号：US07187709B1
公开(公告)日：2007-03-06
申请号：US10090250
申请日：2002-03-01
申请人： Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Paul T. Sasaki , Philip M. Freidin , Santiago G. Asuncion , Philip D. Costello , Vasisht M. Vadi , Adebabay M. Bekele , Hare K. Verma
发明人： Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Paul T. Sasaki , Philip M. Freidin , Santiago G. Asuncion , Philip D. Costello , Vasisht M. Vadi , Adebabay M. Bekele , Hare K. Verma
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： G06F15/7867
摘要： One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.
摘要翻译：一个或多个可配置的收发器可以在集成电路上制造。收发器包含各种组件，具有可通过打开或关闭配置存储单元来配置的选项。该集成电路还可以包含可编程织物。收发器中的其他组件可以具有由可编程结构控制的选项。集成电路还可以包含一个或多个处理器核。处理器核心和收发器可以通过通过可编程结构的多个信号路径连接。

13. 发明授权

US07109746B1 Data monitoring for single event upset in a programmable logic device 有权
标题翻译：可编程逻辑器件中单事件不正常的数据监控
公开(公告)号：US07109746B1
公开(公告)日：2006-09-19
申请号：US10806697
申请日：2004-03-22
申请人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
发明人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/1776
摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.
摘要翻译：描述用于错误检测的数据监视的方法和装置。可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。辅助地址线耦合到与功能发生器相关联的存储器单元组。掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

14. 发明授权

US06822894B1 Single event upset in SRAM cells in FPGAs with leaky gate transistors 有权
标题翻译：具有泄漏栅极晶体管的FPGA中的单元事件不正常
公开(公告)号：US06822894B1
公开(公告)日：2004-11-23
申请号：US10396883
申请日：2003-03-25
申请人： Philip D. Costello , Martin L. Voogel
发明人： Philip D. Costello , Martin L. Voogel
IPC分类号： G11C1100
CPC分类号： G11C11/4125
摘要： A memory device having single event upset (SEU) resistant circuitry includes a first inverter having an input and an output, a second inverter having an input and an output, a first transistor having a gate coupled to the input of the first inverter and having source and drain regions coupled to the output of the second inverter, and a second transistor having a gate coupled to the input of the second inverter and having source and drain regions coupled to the output of the first inverter.
摘要翻译：具有单事件镦粗（SEU）电阻电路的存储器件包括具有输入和输出的第一反相器，具有输入和输出的第二反相器，具有耦合到第一反相器的输入的栅极的第一晶体管，以及耦合到所述第二反相器的输出的漏极区域，以及第二晶体管，其栅极耦合到所述第二反相器的输入并且具有耦合到所述第一反相器的输出的源极和漏极区域。

15. 发明授权

US5173656A Reference generator for generating a reference voltage and a reference current 失效
标题翻译：用于产生参考电压和参考电流的参考发生器
公开(公告)号：US5173656A
公开(公告)日：1992-12-22
申请号：US690446
申请日：1991-04-23
申请人： Evert Seevinck , Philip D. Costello
发明人： Evert Seevinck , Philip D. Costello
IPC分类号： G05F3/26
CPC分类号： G05F3/262 , Y10S323/907
摘要： A reference generator includes a first, a second and an additional third current mirror for generating both a reference output current and a reference output voltage. As the reference output voltage only depends on the gate-source voltages of transistors which are fed with a constant current, the reference output voltage has a constant value and is substantially independent of the ambient temperature.

16. 发明授权

US06911842B1 Low jitter clock for a physical media access sublayer on a field programmable gate array 有权
标题翻译：用于现场可编程门阵列上的物理介质访问子层的低抖动时钟
公开(公告)号：US06911842B1
公开(公告)日：2005-06-28
申请号：US10090239
申请日：2002-03-01
申请人： Atul V. Ghia , Vasisht M. Vadi , Adebabay M. Bekele , Philip D. Costello , Hare K. Verma
发明人： Atul V. Ghia , Vasisht M. Vadi , Adebabay M. Bekele , Philip D. Costello , Hare K. Verma
IPC分类号： G06F1/04 , G06F1/10 , H03K17/693 , H03K19/173 , H03K19/77
CPC分类号： G06F1/10
摘要： A programmable logic device (PLD) is provided that supports multi-gigabit transceivers (MGTs). The PLD includes one or more pairs of shared clock pads for receiving one or more high-quality differential clock signals. Dedicated clock traces couple each pair of shared clock pads to one or more MGTs on the PLD. Each MGT includes a clock multiplexer circuit, which allows one of the high-quality differential clock signals to be routed as a reference clock signal for the MGT. The clock multiplexer circuits are designed such that no significant jitter is added to the high-quality clock signals. The clock multiplexer circuits can also route general-purpose clock signals received by the PLD as lower quality reference clock signals for the MGTs. The reference clock signal routed by the clock multiplexer circuit can be stepped down to provide a reference clock for a physical coding sublayer of the MGT.
摘要翻译：提供了支持多千兆位收发器（MGT）的可编程逻辑器件（PLD）。 PLD包括用于接收一个或多个高质量差分时钟信号的一对或多对共享时钟焊盘。专用时钟跟踪将每对共享时钟接口耦合到PLD上的一个或多个MGT。每个MGT包括时钟多路复用器电路，其允许将高质量差分时钟信号中的一个作为MGT的参考时钟信号进行路由。时钟多路复用器电路被设计成使得高质量时钟信号不会增加显着的抖动。时钟多路复用器电路还可以将由PLD接收的通用时钟信号作为MGT的较低质量参考时钟信号。可以降低由时钟多路复用器电路路由的参考时钟信号，为MGT的物理编码子层提供参考时钟。

17. 发明授权

US06753722B1 Method and apparatus for voltage regulation within an integrated circuit 有权
标题翻译：集成电路内电压调节的方法和装置
公开(公告)号：US06753722B1
公开(公告)日：2004-06-22
申请号：US10354560
申请日：2003-01-30
申请人： Venu M. Kondapalli , Martin L. Voogel , Philip D. Costello
发明人： Venu M. Kondapalli , Martin L. Voogel , Philip D. Costello
IPC分类号： G05F110
CPC分类号： G05F1/56
摘要： Method and apparatus for regulating voltage within an integrated circuit is described. For example, a voltage regulator receives a first reference voltage and produces a regulated voltage. A comparator includes a first input for receiving a second reference voltage and a second input for receiving the regulated voltage. The comparator includes an offset voltage. The comparator produces a control signal indicative of whether the difference between the second reference voltage and the regulated voltage is greater than a predetermined offset voltage. A clamp circuit clamps the regulated voltage to the second reference voltage in response to the control signal. In another example, the clamp circuit is removed and a multiplexer selects either a first reference voltage or a second reference voltage to be coupled to a voltage regulator. The multiplexer is controlled via output of a comparator that compares the first reference voltage and the second reference voltage.
摘要翻译：描述了用于调整集成电路内的电压的方法和装置。例如，电压调节器接收第一参考电压并产生调节电压。比较器包括用于接收第二参考电压的第一输入端和用于接收调节电压的第二输入端。比较器包括偏移电压。比较器产生指示第二参考电压和调节电压之间的差是否大于预定偏移电压的控制信号。钳位电路响应于控制信号将调节电压钳位到第二参考电压。在另一示例中，钳位电路被去除，并且多路复用器选择要耦合到电压调节器的第一参考电压或第二参考电压。通过比较第一参考电压和第二参考电压的比较器的输出来控制多路复用器。

18. 发明授权

US5216291A Buffer circuit having high stability and low quiescent current consumption 失效
标题翻译：具有高稳定性和低电流消耗的缓冲电路
公开(公告)号：US5216291A
公开(公告)日：1993-06-01
申请号：US690445
申请日：1991-04-23
申请人： Evert Seevinck , Philip D. Costello
发明人： Evert Seevinck , Philip D. Costello
IPC分类号： G05F1/56 , G05F1/46 , G05F3/24 , G05F3/26
CPC分类号： G05F3/24 , G05F1/462
摘要： A buffer circuit for buffering an applied reference voltage at a low output impedance. The buffer circuit includes an input transistor which is coupled to an external reference voltage and to an external reference current, and a voltage-to-current converter for applying less or more current to an output terminal of the buffer circuit. This provides a substantially temperature-independent and stable buffer circuit which consumes very little quiescent current.

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