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11. 发明授权

US08441277B2 Semiconductor testing device, semiconductor device, and testing method 失效
标题翻译：半导体测试装置，半导体器件和测试方法
公开(公告)号：US08441277B2
公开(公告)日：2013-05-14
申请号：US12810877
申请日：2008-12-16
申请人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
发明人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
IPC分类号： G01R31/26
CPC分类号： G01R31/31908
摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.
摘要翻译：提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。

12. 发明授权

US08072253B2 Clock adjusting circuit and semiconductor integrated circuit device 失效
标题翻译：时钟调整电路和半导体集成电路器件
公开(公告)号：US08072253B2
公开(公告)日：2011-12-06
申请号：US12440967
申请日：2007-09-11
申请人： Shunichi Kaeriyama , Masayuki Mizuno
发明人： Shunichi Kaeriyama , Masayuki Mizuno
IPC分类号： H03H11/16
CPC分类号： H03L7/0995 , G06F1/08 , H03K5/13 , H03K5/133 , H03K5/1565 , H03K2005/00052 , H03K2005/00058 , H03L7/07 , H03L7/0812 , H03L7/0814 , H03L7/0996 , H03L7/0998 , H04L7/0337
摘要： Disclosed is a clock adjusting circuit comprising a phase shifter that receives a clock signal and variably shifts, based on a control signal, respective timing phases of a rising edge and a falling edge of the clock signal; and a control circuit that supplies the control signal to the phase shifter circuit before each edge is output; wherein the clock signal, in which at least one of a period, a duty ratio, jitter and skew/delay of the input clock signal is changed over an arbitrary number of clock cycles, is output.
摘要翻译：公开了一种时钟调节电路，包括：移相器，其接收时钟信号，并且基于控制信号可变地移位时钟信号的上升沿和下降沿的相应定时相位; 以及控制电路，其在每个边缘被输出之前将所述控制信号提供给所述移相器电路; 其中输出时钟信号，其中输入时钟信号的周期，占空比，抖动和偏移/延迟中的至少一个在任意数量的时钟周期上改变。

13. 发明授权

US07908538B2 Failure prediction circuit and method, and semiconductor integrated circuit 有权
标题翻译：故障预测电路及方法，半导体集成电路
公开(公告)号：US07908538B2
公开(公告)日：2011-03-15
申请号：US12438576
申请日：2007-08-09
申请人： Masayuki Mizuno , Toru Nakura , Koichi Nose
发明人： Masayuki Mizuno , Toru Nakura , Koichi Nose
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/31726 , G01R31/31937
摘要： Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit that determines whether or not the results of the first storage circuit and the second storage circuit coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs.
摘要翻译：公开了一种半导体集成电路，包括：第一存储电路和第二存储电路，其在时钟线的逻辑电平改变时分别存储对延迟电路的输入的逻辑电平和延迟电路的输出;以及确定电路确定第一存储电路和第二存储电路的结果是否一致。即使构成半导体集成电路的晶体管或布线由于长期变化等而劣化，也可以在异常或异常之前预测由劣化引起的运算电路之一的异常或故障的可能性发生故障

14. 发明授权

US07893742B2 Clock signal dividing circuit 有权
标题翻译：时钟信号分频电路
公开(公告)号：US07893742B2
公开(公告)日：2011-02-22
申请号：US12514115
申请日：2007-10-26
申请人： Atsufumi Shibayama , Koichi Nose , Masayuki Mizuno
发明人： Atsufumi Shibayama , Koichi Nose , Masayuki Mizuno
IPC分类号： H03L7/00
CPC分类号： G06F1/10 , H03K23/507 , H03L7/0814 , H03L7/16
摘要： A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit.
摘要翻译：分频比由N / M（M和N是正整数，满足M> N）调节的时钟信号分频电路包括：可变延迟电路，其基于对输入时钟的控制值给出预定的延迟量信号CKI输出输出时钟信号CKO; 以及可变延迟控制电路，当相加结果为N以上时，累积地将通过从输入时钟信号CKI的每个周期从M中减去N而获得的值执行从相加结果中减去N的计算，以获得计算结果K ，并且将对应于输入时钟信号CKI的一个周期的可变延迟电路中的最大延迟量计算为与最大延迟量的K / N的延迟量相对应的控制值，以将控制值赋予该变量延时电路。

15. 发明授权

US07872524B2 Amplification circuit, amplification circuit noise reducing method and program thereof 有权
标题翻译：放大电路，放大电路降噪方法及程序
公开(公告)号：US07872524B2
公开(公告)日：2011-01-18
申请号：US12439971
申请日：2007-09-13
申请人： Haruya Ishizaki , Masayuki Mizuno
发明人： Haruya Ishizaki , Masayuki Mizuno
IPC分类号： H03F1/36
CPC分类号： H03F1/22 , H03F3/189 , H03H7/24 , H03H11/245
摘要： [Problems] to provide a CMOS low-noise amplification circuit which can reduce a chip area and design time, and which is easy to be digital-controlled from outside. [Means For Solving the Problems] The amplification circuit includes; an amplification stage (12) which amplifies an input signal up to an intended value; a sample and hold circuit (13) which samples the output signal from the amplification stage (12) by sampling the output signal with a sampling frequency which is at least twice the frequency band of the output signal to convert the output signal to a discrete time signal; a moving average calculation unit (15) which selects and outputs a particular frequency from the discrete time signal outputted from the sample and hold circuit (13) by a moving average operation; and a smoothing filter (17) which smoothes the output signal from the moving average calculation unit (15) and feed it back to the input of the amplification stage (12).
摘要翻译： [问题]提供可以减少芯片面积和设计时间的CMOS低噪声放大电路，并且易于从外部数字控制。解决问题的手段放大电路包括：放大级（12），其将输入信号放大到预期值; 采样和保持电路（13），其通过以至少是输出信号的频带的两倍的采样频率对输出信号进行采样来对来自放大级（12）的输出信号进行采样，以将输出信号转换为离散时间信号; 移动平均计算单元（15），其通过移动平均操作从采样和保持电路（13）输出的离散时间信号中选择并输出特定频率; 以及平滑滤波器（17），其平滑来自移动平均计算单元（15）的输出信号并将其馈送回到放大级（12）的输入端。

16. 发明申请

US20100272149A1 TEMPERATURE MEASURING DEVICE AND METHOD 失效
标题翻译：温度测量装置及方法
公开(公告)号：US20100272149A1
公开(公告)日：2010-10-28
申请号：US12746947
申请日：2008-11-27
申请人： Eisuke Saneyoshi , Koichi Nose , Mikihiro Kajita , Masayuki Mizuno
发明人： Eisuke Saneyoshi , Koichi Nose , Mikihiro Kajita , Masayuki Mizuno
IPC分类号： G01K13/00
CPC分类号： G01K7/01 , G01K2219/00
摘要： Current reading means detects an output current of a current source whose output current varies with a variation in temperature and outputs a value proportional to the output current. The temperature of the current source corresponding to the output value of the current reading means which is proportional to the output current of the current source is measured, and a parameter for converting the output value to temperature information is determined from the output value of the current reading means and the measured value of the temperature of the current source corresponding to the output value. The output value of the current reading means is converted to the temperature information using the determined parameter.
摘要翻译：电流读取装置检测输出电流随温度变化而变化的电流源的输出电流，并输出与输出电流成比例的值。测量与电流读取装置的输出值对应的电流源的温度，其与电流源的输出电流成比例，并且根据电流的输出值确定将输出值转换为温度信息的参数读数手段和对应于输出值的电流源的温度测量值。使用所确定的参数将电流读取装置的输出值转换为温度信息。

17. 发明申请

US20100176893A1 MODULATION DEVICE AND PULSE WAVE GENERATION DEVICE 有权
标题翻译：调制装置和脉冲波生成装置
公开(公告)号：US20100176893A1
公开(公告)日：2010-07-15
申请号：US12602869
申请日：2008-06-06
申请人： Koichi Nose , Haruya Ishizaki , Masayuki Mizuno
发明人： Koichi Nose , Haruya Ishizaki , Masayuki Mizuno
IPC分类号： H03C3/00
CPC分类号： H04L27/20 , H03K5/13 , H03K5/156 , H03K2005/00052 , H04L27/12
摘要： Provided is a modulation device including a signal selection circuit selecting two carrier signals from a plurality of carrier signals having the same frequency and the same phase difference according to a defined control signal and outputting the selected carrier signals, and a phase interpolator adjusting the phase in smaller units than the phase difference between the plurality of carrier signals according to the control signal and modulating the frequency or the phase of the carrier signal into a baseband signal based on the carrier signals selected by the signal selection circuit to generate a carrier wave signal.
摘要翻译：提供了一种调制装置，其包括信号选择电路，根据定义的控制信号从具有相同频率和相同相位差的多个载波信号中选择两个载波信号并输出所选择的载波信号;以及相位内插器，根据控制信号比多个载波信号之间的相位差小的单位，并且基于由信号选择电路选择的载波信号将载波信号的频率或相位调制成基带信号，以产生载波信号。

18. 发明申请

US20100100886A1 TASK GROUP ALLOCATING METHOD, TASK GROUP ALLOCATING DEVICE, TASK GROUP ALLOCATING PROGRAM, PROCESSOR AND COMPUTER 有权
标题翻译：任务组分配方法，任务组分配设备，任务组分配程序，处理器和计算机
公开(公告)号：US20100100886A1
公开(公告)日：2010-04-22
申请号：US12529367
申请日：2008-02-05
申请人： Masamichi Takagi , Masayuki Mizuno , Hiroaki Inoue
发明人： Masamichi Takagi , Masayuki Mizuno , Hiroaki Inoue
IPC分类号： G06F9/50
CPC分类号： G06F9/5027 , G06F11/1428 , G06F11/3419 , G06F11/3433 , G06F2209/483 , G06F2209/501
摘要： Even if a multiprocessor includes an uneven performance core, an inoperative core or a core that does not satisfy such a performance as designed but if the contrivance of task allocation can satisfy the requirement of an application to be executed, the multiple processors are shipped. In a task group allocation method for allocating, to a processor having a plurality of cores, task groups included in an application for the processor to execute, a calculation section measures performances and disposition patterns of the cores, generates a restricting condition associating the measured performances and disposition patterns of the cores with information indicating whether the application can be executed, and, with reference to the restricting condition, reallocates to the cores, the task groups that have previously been allocated to the cores.
摘要翻译：即使多处理器包括不均衡的性能核心，不能满足设计性能的不工作核心或核心，但如果任务分配的设计能够满足执行应用程序的要求，则会发送多个处理器。在用于将具有多个核心的处理器分配给应用程序中的处理器执行的任务组的任务组分配方法中，计算部分测量核心的性能和配置模式，产生将测量性能以及具有指示是否可以执行应用的信息的核心的配置模式，并且参考限制条件将已经分配给核心的任务组重新分配给核心。

19. 发明授权

US07702945B2 Semiconductor device and communication control method 有权
标题翻译：半导体器件和通信控制方法
公开(公告)号：US07702945B2
公开(公告)日：2010-04-20
申请号：US11575473
申请日：2005-09-16
申请人： Atsufumi Shibayama , Koichi Nose , Masayuki Mizuno
发明人： Atsufumi Shibayama , Koichi Nose , Masayuki Mizuno
IPC分类号： G06F1/04
CPC分类号： H04L7/0012 , G06F1/12 , H04L7/0041
摘要： The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B. The controller controls in such way that the core B can receive only the data arriving prior to the setup of the clock signal clkB. The controller stores the history on a communication status between cores.
摘要翻译：本发明涉及能够建立核之间的通信的技术，其能够提供可在每个核心中设置的时钟频率的大的自由度，从而提供确定性的操作，小的通信延迟和高的可靠性。本发明的目的是通过基于半导体器件内的通信历史分析影响半导体器件的性能的因素，并将分析反映到下一代半导体器件，来提供具有高可靠性的半导体器件。改进的半导体器件包括用于与时钟信号clkA同步发送数据的核心A，用于接收与时钟信号clkB同步的数据的核心B与时钟信号clkA的上升或下降保持一致，并且控制器用于控制核心A和核心B之间的通信。控制器以这样的方式进行控制，使得核心B可以仅接收在建立时钟信号clkB之前到达的数据。控制器将历史记录存储在内核之间的通信状态。

20. 发明申请

US20100042373A1 SIGNAL MEASURING DEVICE AND SIGNAL MEASURING METHOD 失效
标题翻译：信号测量装置和信号测量方法
公开(公告)号：US20100042373A1
公开(公告)日：2010-02-18
申请号：US12519837
申请日：2007-12-19
申请人： Koichi Nose , Masayuki Mizuno , Atsufumi Shibayama
发明人： Koichi Nose , Masayuki Mizuno , Atsufumi Shibayama
IPC分类号： G06F15/00
CPC分类号： G01R31/31937 , G01R31/31708 , G01R31/31726
摘要： A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.
摘要翻译：一种信号测量装置，包括测量与测量的驱动时钟信号同步的测量对象的一组或多组测量单元，并将测量结果作为第一数据输出，以及定时识别单元，根据测量开始命令，将与每个周期不同的值作为与具有规定周期和速度低于驱动时钟信号的参考信号同步的第二数据输出; 以及与所述驱动时钟信号同步地收集并依次存储所述第一数据和所述第二数据作为一组的存储单元。

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