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11. 发明授权

US07900071B2 Apparatus and method to manage power in a computing device 失效
标题翻译：在计算设备中管理功率的装置和方法
公开(公告)号：US07900071B2
公开(公告)日：2011-03-01
申请号：US12031543
申请日：2008-02-14
申请人： Robert H. Bell, Jr. , Jose Raul Escalera , Octavian Florin Herescu , Vernon Walter Miller , Michael Declan Roll
发明人： Robert H. Bell, Jr. , Jose Raul Escalera , Octavian Florin Herescu , Vernon Walter Miller , Michael Declan Roll
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , Y02D10/16
摘要： A method to manage power in a computing device comprising a controller assembly and a storage assembly comprising a plurality of data storage devices, by selecting a processor parameter, establishing a threshold processor parameter value, establishing a threshold over-parameter time interval, selecting a data storage device parameter, and establishing a nominal data storage device parameter value. The method determines an actual processor parameter value. If the actual processor parameter value is less than or equal to the threshold processor parameter value, the method operates each of the plurality of data storage devices using the nominal data storage device parameter value. If the actual processor parameter value is greater than the threshold processor parameter value, then the method determines an actual over-parameter time interval. If the actual processor parameter value is greater than the threshold processor parameter value, and if the actual over-parameter time interval is greater than the threshold over-parameter time interval, then the method operates each of the plurality of data storage devices using a data storage device parameter value less than the nominal data storage device parameter value.
摘要翻译：一种通过选择处理器参数，建立阈值处理器参数值，建立阈值超参数时间间隔，选择数据的方法来管理计算设备中的功率的方法，包括控制器组件和包括多个数据存储设备的存储组件存储设备参数，并建立标称数据存储设备参数值。该方法确定实际的处理器参数值。如果实际处理器参数值小于或等于阈值处理器参数值，则该方法使用标称数据存储设备参数值来操作多个数据存储设备中的每一个。如果实际处理器参数值大于阈值处理器参数值，则该方法确定实际的超参数时间间隔。如果实际处理器参数值大于阈值处理器参数值，并且如果实际超参数时间间隔大于阈值过参数时间间隔，则该方法使用数据来操作多个数据存储设备中的每一个存储设备参数值小于额定数据存储设备参数值。

12. 发明授权

US07840758B2 Variable store gather window 有权
标题翻译：变量存储收集窗口
公开(公告)号：US07840758B2
公开(公告)日：2010-11-23
申请号：US11689990
申请日：2007-03-22
申请人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
发明人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译：处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

13. 发明授权

US07543109B1 System and method for caching data in a blade server complex 失效
标题翻译：用于在刀片服务器组合中缓存数据的系统和方法
公开(公告)号：US07543109B1
公开(公告)日：2009-06-02
申请号：US12122448
申请日：2008-05-16
申请人： Robert H. Bell, Jr. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
发明人： Robert H. Bell, Jr. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
IPC分类号： G06F12/02
CPC分类号： G06F12/126 , G06F12/0888
摘要： A method for caching data in a blade computing complex includes providing a storage blade that includes a disk operative to store pages of data and a cache memory operative to store at least one of the pages. A processor blade is provided that includes a first memory area to store at least one of the pages and a second memory area configured to store an address of each of the pages and a hint value that is assigned to each of the pages. An address of each of the pages is stored in the second memory area, and a hint is assigned to each of the pages, where the hint is one of: likely to be accessed, may be accessed, and unlikely to be accessed. The page is then stored in storage blade cache memory based on the hint.
摘要翻译：一种用于在刀片计算复合体中缓存数据的方法包括提供包括可操作以存储数据页的盘的存储刀片和可存储至少一个页的高速缓冲存储器。提供了一种处理器刀片，其包括用于存储所述页面中的至少一个的第一存储器区域和被配置为存储每个页面的地址的第二存储器区域以及分配给每个页面的提示值。每个页面的地址被存储在第二存储器区域中，并且提示被分配给每个页面，其中提示是可能被访问的，可能被访问并且不可能被访问。然后基于提示将该页面存储在存储刀片缓存中。

14. 发明授权

US07363433B2 Cache member protection with partial make MRU allocation 失效
标题翻译：缓存成员保护部分使MRU分配
公开(公告)号：US07363433B2
公开(公告)日：2008-04-22
申请号：US11054390
申请日：2005-02-09
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下，否定受保护成员的选择。

15. 发明授权

US06950892B2 Method and system for managing distributed arbitration for multicycle data transfer requests 失效
标题翻译：用于管理多周期数据传输请求的分布式仲裁的方法和系统
公开(公告)号：US06950892B2
公开(公告)日：2005-09-27
申请号：US10411463
申请日：2003-04-10
申请人： Robert H. Bell, Jr. , Robert Alan Cargnoni
发明人： Robert H. Bell, Jr. , Robert Alan Cargnoni
IPC分类号： G06F13/372 , G06F12/00 , G06F12/08 , G06F13/14 , G06F13/364 , G06F13/368
CPC分类号： G06F13/364 , G06F12/0846
摘要： A method and system for managing distributed arbitration for multi-cycle data transfer requests provides improved performance in a processing system. A multi-cycle request indicator is provided to a slice arbiter and if a multi-cycle request is present, only one slice is granted its associated bus. The method further blocks any requests from other requesting slices having a lower latency than the first slice until the latency difference between the other requesting slices and the longest latency slice added to a predetermined cycle counter value has expired. The method also blocks further requests from the first slice until the predetermined cycle counter value has elapsed and blocks requests from slices having a higher latency than the first slice until the predetermined cycle counter value less the difference in latencies for the first slice and for the higher latency slice has elapsed.
摘要翻译：用于管理多循环数据传输请求的分布式仲裁的方法和系统在处理系统中提供改善的性能。多周期请求指示符被提供给切片仲裁器，并且如果存在多周期请求，则只有一个切片被授予其相关联的总线。该方法进一步阻止来自具有比第一片低的等待时间的其他请求片的任何请求，直到其他请求片之间的等待时间差与添加到预定周期计数值的最长等待时间片已经期满为止。该方法还阻止来自第一片的进一步请求，直到经过了预定周期计数器值，并且阻止来自具有比第一片的更高等待时间的片的请求，直到预定周期计数值减去第一片的延迟差和较高延迟片已过。

16. 发明授权

US09582284B2 Performance of processors is improved by limiting number of branch prediction levels 有权
标题翻译：通过限制分支预测级别的数量来提高处理器的性能
公开(公告)号：US09582284B2
公开(公告)日：2017-02-28
申请号：US13308696
申请日：2011-12-01
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen
IPC分类号： G06F9/38 , G06F11/30
CPC分类号： G06F9/3844 , G06F9/3842 , G06F11/30 , G06F11/3024 , G06F11/3409 , G06F2201/81
摘要： A method utilizes information provided by performance monitoring hardware to dynamically adjust the number of levels of speculative branch predictions allowed (typically 3 or 4 per thread) for a processor core. The information includes cycles-per-instruction (CPI) for the processor core and number of memory accesses per unit time. If the CPI is below a CPI threshold; and the number of memory accesses (NMA) per unit time is above a prescribed threshold, the number of levels of speculative branch predictions is reduced per thread for the processor core. Likewise, the number of levels of speculative branch predictions could be increased, from a low level to maximum allowed, if the CPI threshold is exceeded or the number of memory accesses per unit time is below the prescribed threshold.
摘要翻译：一种方法利用由性能监视硬件提供的信息来动态调整对于处理器核心允许的推测分支预测级别（通常为每线程3或4个）。该信息包括处理器核心的每个指令周期（CPI）和每单位时间的存储器访问次数。如果CPI低于CPI阈值; 并且每单位时间的存储器访问次数（NMA）高于规定的阈值，则对于处理器核，每个线程的推测分支预测的级别数量减少。同样地，如果超过CPI阈值或每单位时间的存储器访问次数低于规定的阈值，则可以将推测分支预测的级数从低级别增加到允许的最大级别。

17. 发明授权

US09298458B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
公开(公告)号：US09298458B2
公开(公告)日：2016-03-29
申请号：US13427083
申请日：2012-03-22
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

18. 发明授权

US08943272B2 Variable cache line size management 有权
标题翻译：可变缓存行大小管理
公开(公告)号：US08943272B2
公开(公告)日：2015-01-27
申请号：US13451742
申请日：2012-04-20
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line from an upper level sectored cache to an unsectored lower level cache is to be performed, wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache; responsive to determining that an eviction is to be performed, identifying referenced sub-sectors of the cache line to be evicted; invalidating unreferenced sub-sectors of the cache line to be evicted; and storing the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的方法和技术。该方法包括：确定是否执行将高速缓存行从高级扇区高速缓存驱逐到未故障的较低级高速缓存，其中高级缓存包括多个子扇区，每个子扇区具有高速缓存行对应于较低级缓存的高速缓存行大小的大小; 响应于确定要执行驱逐，识别要被驱逐的高速缓存行的参考子扇区; 使要删除的缓存行的未引用子扇区无效; 并将所引用的子扇区存储在下级缓存中。

19. 发明授权

US08769210B2 Dynamic prioritization of cache access 有权
标题翻译：高速缓存访问的动态优先级
公开(公告)号：US08769210B2
公开(公告)日：2014-07-01
申请号：US13323076
申请日：2011-12-12
申请人： Robert H. Bell, Jr. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/0815
摘要： Some embodiments of the inventive subject matter are directed to a cache comprising a tracking unit and cache state machines. In some embodiments, the tracking unit is configured to track an amount of cache resources used to service cache misses within a past period. In some embodiments, each of the cache state machines is configured to, determine whether a memory access request results in a cache miss or cache hit, and in response to a cache miss for a memory access request, query the tracking unit for the amount of cache resources used to service cache misses within the past period. In some embodiments, the each of the cache state machines is configured to service the memory access request based, at least in part, on the amount of cache resources used to service the cache misses within the past period according to the tracking unit.
摘要翻译：本发明主题的一些实施例涉及包括跟踪单元和高速缓存状态机的高速缓存。在一些实施例中，跟踪单元被配置为跟踪用于在过去时间段内服务高速缓存未命中的高速缓存资源的量。在一些实施例中，每个高速缓存状态机被配置为，确定存储器访问请求是否导致高速缓存未命中或高速缓存命中，并且响应于存储器访问请求的高速缓存未命中，查询跟踪单元的数量用于在过去一段时间内缓存未命中服务的缓存资源。在一些实施例中，每个高速缓存状态机被配置为至少部分地基于用于根据跟踪单元在过去时段内服务高速缓存未命中的高速缓存资源的量来服务存储器访问请求。

20. 发明授权

US08527956B2 Workload performance projection via surrogate program analysis for future information handling systems 失效
标题翻译：通过代理程序分析进行未来信息处理系统的工作负载性能预测
公开(公告)号：US08527956B2
公开(公告)日：2013-09-03
申请号：US12343467
申请日：2008-12-23
申请人： Robert H. Bell, Jr. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
发明人： Robert H. Bell, Jr. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
IPC分类号： G06F9/44
CPC分类号： G06F11/3419 , G06F11/3414 , G06F11/3457 , G06F2201/865 , G06F2201/88
摘要： A performance projection system includes a test IHS and multiple currently existing IHSs. The performance projection system includes user application software and surrogate programs that execute on currently existing IHSs. The performance projection system measures user application software and surrogate program performance during execution on currently existing IHSs. The performance projection systems measures runtime program performance during execution of surrogate programs on a future semiconductor die IC design model or virtualized future system. Designers normalize and compare surrogate program runtime performance data with user application software performance data. Designers un-normalize the normalized runtime performance data to generate a projection of runtime performance on the future system.
摘要翻译：性能投影系统包括测试IHS和多个当前存在的IHS。性能投影系统包括在当前存在的IHS上执行的用户应用软件和代理程序。性能投影系统在目前现有的IHSs的执行过程中测量用户应用软件和代理程序性能。性能投影系统在未来的半导体芯片IC设计模型或虚拟化未来系统执行替代程序期间测量运行时程序性能。设计师将代理程序运行时性能数据与用户应用软件性能数据进行规范化和比较。设计师对规范化的运行时性能数据进行非规范化，以生成对未来系统的运行时性能的投影。

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