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11. 发明授权

US07656742B2 Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
标题翻译：在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US07656742B2
公开(公告)日：2010-02-02
申请号：US12128464
申请日：2008-05-28
申请人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
IPC分类号： G11C8/00
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

12. 发明申请

US20080144406A1 Memory system, memory device, and output data strobe signal generating method 失效
标题翻译：存储器系统，存储器件和输出数据选通信号生成方法
公开(公告)号：US20080144406A1
公开(公告)日：2008-06-19
申请号：US12071347
申请日：2008-02-20
申请人： Kwang-ll Park , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-ll Park , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.
摘要翻译：输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导信号。

13. 发明授权

US06809546B2 On-chip termination apparatus in semiconductor integrated circuit, and method for controlling the same 失效
标题翻译：半导体集成电路中的片上终端装置及其控制方法
公开(公告)号：US06809546B2
公开(公告)日：2004-10-26
申请号：US10287136
申请日：2002-11-04
申请人： Ho-Young Song , Seong-jin Jang
发明人： Ho-Young Song , Seong-jin Jang
IPC分类号： H03K1716
CPC分类号： H04L25/0278 , H03K19/018592
摘要： Provided are an on-chip termination apparatus in a semiconductor integrated circuit, and a method for controlling the same. The on-chip termination apparatus is installed in a semiconductor integrated circuit that has an output driver for outputting data to the outside via a pad and a data input circuit for receiving data from the outside via the pad. The on-chip termination apparatus includes an on-chip terminator including at least one terminal resistor electrically connected to the pad; and a terminator control circuit for turning on or off the on-chip terminator in response to an output enable signal that enables or disables the data output circuit, wherein the terminator control circuit turns off the on-chip terminator in the event that the data output circuit is enabled. Therefore, the on-chip termination apparatus is controlled by an output enable signal, thereby reducing timing loss, thus enabling a system to operate at high speed.
摘要翻译：提供一种半导体集成电路中的片上终端装置及其控制方法。片上终端装置安装在半导体集成电路中，该半导体集成电路具有用于经由焊盘向外部输出数据的输出驱动器和用于经由焊盘从外部接收数据的数据输入电路。片上终端装置包括片上终端器，其包括电连接到该焊盘的至少一个端子电阻器; 以及用于响应于使能或禁止数据输出电路的输出使能信号来接通或关断片上终端器的终端控制电路，其中在数据输出的情况下，终端控制电路关断片上终端器电路启用。因此，片上终端装置由输出使能信号控制，从而减少定时损耗，从而使得系统能够以高速运行。

14. 发明授权

US07814359B2 High-speed phase-adjusted quadrature data rate (QDR) transceiver and method thereof 有权
标题翻译：高速相位调整正交数据速率（QDR）收发器及其方法
公开(公告)号：US07814359B2
公开(公告)日：2010-10-12
申请号：US11612800
申请日：2006-12-19
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-Il Park , Sang-Woong Shin , Ho-Young Song
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-Il Park , Sang-Woong Shin , Ho-Young Song
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.
摘要翻译：提供了一种高速双倍或正交数据速率接口半导体器件及其方法。用于高速数据传输的发射机（例如，数据传输半导体器件）发射第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和第二组（字节）数据。发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

15. 发明授权

US08004911B2 Memory system, memory device, and output data strobe signal generating method 失效
标题翻译：存储器系统，存储器件和输出数据选通信号生成方法
公开(公告)号：US08004911B2
公开(公告)日：2011-08-23
申请号：US12662720
申请日：2010-04-29
申请人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.
摘要翻译：输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导信号。

16. 发明授权

US07362648B2 Memory system, memory device, and output data strobe signal generating method 有权
公开(公告)号：US07362648B2
公开(公告)日：2008-04-22
申请号：US11251787
申请日：2005-10-18
申请人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

17. 发明申请

US20060083081A1 Memory system, memory device, and output data strobe signal generating method 有权
标题翻译：存储器系统，存储器件和输出数据选通信号生成方法
公开(公告)号：US20060083081A1
公开(公告)日：2006-04-20
申请号：US11251787
申请日：2005-10-18
申请人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.
摘要翻译：输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导信号。

18. 发明授权

US07733715B2 Memory system, memory device, and output data strobe signal generating method 失效
标题翻译：存储器系统，存储器件和输出数据选通信号生成方法
公开(公告)号：US07733715B2
公开(公告)日：2010-06-08
申请号：US12071347
申请日：2008-02-20
申请人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.
摘要翻译：输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导码信号。

19. 发明授权

US07394720B2 Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
标题翻译：在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US07394720B2
公开(公告)日：2008-07-01
申请号：US11560746
申请日：2006-11-16
申请人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
IPC分类号： G11C8/00
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

20. 发明申请

US20060066364A1 Input buffer having a stabilized operating point and an associated method 失效
标题翻译：输入缓冲器具有稳定的工作点和相关联的方法
公开(公告)号：US20060066364A1
公开(公告)日：2006-03-30
申请号：US11225915
申请日：2005-09-13
申请人： Hyun-Jin Kim , Seong-Jin Jang , Kwang-Il Park , Sang-Joon Hwang , Ho-Young Song , Ho-Kyong Lee , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Kwang-Il Park , Sang-Joon Hwang , Ho-Young Song , Ho-Kyong Lee , Woo-Jin Lee
IPC分类号： H03B1/00
CPC分类号： H03F3/45
摘要： We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.
摘要翻译：我们描述具有稳定的工作点和相关方法的输入缓冲器。输入缓冲器可以包括：第一差分放大单元，用于产生具有第一工作点的第一输出信号和第二差分放大单元，以产生具有第二工作点的第二输出信号。响应于输出控制信号，输出控制电路改变第一和第二输出信号的各个权重。第一差分放大单元可以响应于参考电压和输入电压信号而进行操作。第二差分放大单元可以响应于参考电压和输入电压信号而工作。第一工作点可以相对高于第二工作点。

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