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11. 发明申请

US20070203962A1 Methods and apparatus for providing a booth multiplier 失效
标题翻译：提供展位乘数的方法和装置
公开(公告)号：US20070203962A1
公开(公告)日：2007-08-30
申请号：US11509492
申请日：2006-08-24
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06J1/00
CPC分类号： G06F7/5332 , G06F7/5338
摘要： Methods and apparatus for converting a radix 2 multiplier to respective groups of radix 4 encoded bits representing numbers of the group consisting of −2, −1, 0, 1, 2, wherein the set of encoded bits includes: a first bit that is true when the associated number is 2, a second bit that is true when the associated number is −2, a third bit that is true when the associated number is either negative or zero, and a fourth bit that is true when the associated number has an absolute value of 1.
摘要翻译：用于将基数2乘法器转换成表示由-2，-1,0,1,2组成的组的编号的基数4编码比特的组的方法和装置，其中编码比特组包括：第一比特，其为真当相关联的号码为2时，当相关号码为-2时为第二位，当相关号码为负号或零时为真的第三位，当关联号码为绝对值1。

12. 发明申请

US20130063206A1 INTEGRATED CIRCUIT 有权
标题翻译：集成电路
公开(公告)号：US20130063206A1
公开(公告)日：2013-03-14
申请号：US13571613
申请日：2012-08-10
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： H01L25/00
CPC分类号： G06F1/10
摘要： Disclosed herein is an integrated circuit including: a timing signal distribution circuit configured to distribute a timing signal that indicates predetermined timing; a synchronous operation circuit configured to operate in synchronization with the distributed timing signal; a logic circuit configured to perform predetermined logical operation based on an operation result of the synchronous operation circuit; and a power supply section configured to supply a voltage lower than a timing signal distribution circuit drive voltage to drive the timing signal distribution circuit as a logic circuit drive voltage to the logic circuit.
摘要翻译：这里公开了一种集成电路，包括：定时信号分配电路，被配置为分配指示预定定时的定时信号; 配置为与所述分布式定时信号同步地操作的同步运算电路; 逻辑电路，被配置为基于所述同步运算电路的运算结果来执行预定的逻辑运算; 以及电源部，被配置为提供低于定时信号分配电路驱动电压的电压，以将定时信号分配电路驱动为逻辑电路的逻辑电路驱动电压。

13. 发明授权

US07926023B2 Methods and apparatus for handling processing errors in a multi-processing system 有权
标题翻译：用于处理多处理系统中的处理错误的方法和装置
公开(公告)号：US07926023B2
公开(公告)日：2011-04-12
申请号：US11999687
申请日：2007-12-06
申请人： Yasukichi Okawa , Daisuke Hiraoka , Koji Hirairi , Tatsuya Koyama
发明人： Yasukichi Okawa , Daisuke Hiraoka , Koji Hirairi , Tatsuya Koyama
IPC分类号： G06F9/44
CPC分类号： G06F11/203 , G06F9/505 , G06F11/2035 , G06F11/2043
摘要： Methods and apparatus are provided for: monitoring processor tasks and associated processor loads therefor that are allocated to be performed by respective sub-processing units associated with a main processing unit; detecting whether a processing error has occurred in a given one of the sub-processing units; re-allocating all of the processor tasks of the given sub-processing unit to one or more participating sub-processing units, including other sub-processing units associated with the main processing unit, based on the processor loads of the processor tasks of the given sub-processing unit and the processor loads of the participating sub-processing units; and at least one of: (i) shutting down, and (ii) re-booting the given sub-processing unit.
摘要翻译：提供了方法和装置，用于：监视分配为由与主处理单元相关联的相应子处理单元执行的处理器任务及其相关联的处理器负载; 检测在给定的一个子处理单元中是否发生了处理错误; 基于给定的处理器任务的处理器负载，将给定子处理单元的所有处理器任务的所有处理器任务重新分配给一个或多个参与子处理单元，包括与主处理单元相关联的其他子处理单元子处理单元和参与子处理单元的处理器负载; 以及至少一个：（i）关闭，和（ii）重新启动给定的子处理单元。

14. 发明授权

US07720902B2 Methods and apparatus for providing a reduction array 失效
标题翻译：用于提供还原阵列的方法和装置
公开(公告)号：US07720902B2
公开(公告)日：2010-05-18
申请号：US11509532
申请日：2006-08-24
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F7/50
CPC分类号： G06F7/509 , G06F7/53 , G06F7/5443
摘要： Methods and apparatus provide for accumulating bit streams from four partial products and producing a carry-save output pair, including: producing the save, S, portion of the carry-save output pair, in accordance with the following Boolean expression: S=d3 XOR ((d0 XOR d1) XOR (d2 XOR Cin)), wherein d0, d1, d2, d3 are the bit streams from the four partial products, and Cin is a carry in bit stream receivable from an adjacent compression circuit of an overall partial product reduction array.
摘要翻译：方法和装置提供用于从四个部分乘积积累比特流并产生进位保存输出对，包括：根据以下布尔表达式产生进位保存输出对的保存S部分：S = d3 XOR （（d0 XOR d1）XOR（d2 XOR Cin）），其中d0，d1，d2，d3是来自四个部分乘积的比特流，并且Cin是可从总部分的相邻压缩电路接收的比特流中的进位产品减少阵列。

15. 发明授权

US06480942B1 Synchronized FIFO memory circuit 失效
标题翻译：同步FIFO存储器电路
公开(公告)号：US06480942B1
公开(公告)日：2002-11-12
申请号：US09320720
申请日：1999-05-27
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F1200
CPC分类号： G06F5/12 , G06F2205/126
摘要： A synchronized FIFO memory circuit includes a random access memory and a FIFO controller having a decreased critical-path length. The synchronized FIFO circuit comprises a first counter for counting a number representing a Read Pointer, a second counter for counting a number representing a Write Pointer, a third counter for holding and managing the number of remaining empty entries in the FIFO memory circuit, and comparison means for comparing the value of the third counter with a constant value. Write Ready, Read Ready, Full, Empty, Almost Full and Almost Empty which are status signals of the FIFO memory circuit are produced at a high speed by comparison carried out by the comparison means without using a subtractor.
摘要翻译：同步FIFO存储器电路包括随机存取存储器和具有减小的临界路径长度的FIFO控制器。同步FIFO电路包括用于对表示读指针的数字进行计数的第一计数器，用于计数表示写指针的数的第二计数器，用于保存和管理FIFO存储器电路中的剩余空条目数的第三计数器，以及比较用于将第三计数器的值与常数值进行比较的装置。通过比较而不使用减法器进行比较，通过比较来高速地产生作为FIFO存储器电路的状态信号的写入就绪，准备就绪，充满，空，几乎全部和几乎为空。

16. 发明授权

US6028987A Method of operation of arithmetic and logic unit, storage medium, and arithmetic and logic unit 失效
标题翻译：算术逻辑单元，存储介质和算术逻辑单元的操作方法
公开(公告)号：US6028987A
公开(公告)日：2000-02-22
申请号：US992847
申请日：1997-12-18
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F9/38 , G06F7/00 , G06F7/02 , G06F7/50 , G06F7/544 , G06F7/74 , G06F17/50
CPC分类号： G06F7/74 , G06F7/026 , G06F7/508 , G06F7/544 , G06F2207/5063
摘要： A method of operation of an arithmetic and logic unit, a storage medium, and an arithmetic and logic unit introducing a technique and concept of converting a serial structure of decisions having an order dependency to an indeterminate code binary tree which can be processed in parallel so as to simplify the configuration and enable higher speed operation processing.Where a serial structure of decisions having an order dependency is converted to a binary tree structure using decision nodes not having dependency input/outputs as leaves and higher priority determination nodes as the nodes other than the leaves, the decision nodes having dependency input/outputs are replaced by decision nodes not having dependency input/outputs provided with connotation decision nodes and indeterminate code generation nodes.
摘要翻译：算术和逻辑单元，存储介质和算术和逻辑单元的操作方法，引入将具有顺序依赖性的决定的串行结构转换为可以并行处理的不确定代码二进制树的技术和概念以简化配置并实现更高速度的操作处理。在具有顺序依赖性的决策的串行结构使用不具有依赖输入/输出的判定节点作为叶片和较高优先级确定节点作为除了叶子之外的节点被转换为二进制树结构的情况下，具有相关输入/输出的判定节点是由不具有内含决策节点和不确定代码生成节点提供的依赖输入/输出的决策节点代替。

17. 发明授权

US08874978B2 Information processing apparatus, information processing system, controlling method for information processing apparatus and program 有权
标题翻译：信息处理装置，信息处理系统，信息处理装置和程序的控制方法
公开(公告)号：US08874978B2
公开(公告)日：2014-10-28
申请号：US13416431
申请日：2012-03-09
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F11/00 , G01R31/30 , H03M13/00 , G06F11/10 , G06F1/32 , G06F11/07 , H04L1/20 , G01R31/317 , G01R31/3181 , H03M13/09
CPC分类号： G06F11/1008 , G01R31/3171 , G01R31/31816 , G06F1/324 , G06F1/3296 , G06F11/076 , H03M13/09 , H04L1/203 , Y02D10/126 , Y02D10/172
摘要： An information processing apparatus includes a first parity production section for producing a first error detection code for detecting an error of data. A second parity production section produces a second error detection code for detecting an error of the data from the first error detection code. A first parity checking section detects an error of the retained data as a first error using the retained first error detection code. A second parity checking section detects an error of the retained data as a second error using the retained second error detection code. A control amount outputting section outputs, when an occurrence rate of a first error is equal to or lower than a first threshold value, a control amount for controlling a power supply voltage or a frequency using a second threshold value as a target value for an occurrence rate of a second error.
摘要翻译：信息处理设备包括：第一奇偶校验生成部分，用于产生用于检测数据错误的第一错误检测码。第二奇偶校验生成部分产生用于检测来自第一错误检测码的数据的错误的第二错误检测码。第一奇偶校验部分使用保留的第一错误检测码来检测保留数据的错误作为第一错误。第二奇偶校验部分使用保留的第二错误检测码来检测作为第二错误的保留数据的错误。当第一误差的出现率等于或低于第一阈值时，控制量输出部分输出用于使用第二阈值控制电源电压或频率的控制量作为发生的目标值率的第二个错误。

18. 发明申请

US20120254676A1 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, CONTROLLING METHOD FOR INFORMATION PROCESSING APPARATUS AND PROGRAM 有权
标题翻译：信息处理装置，信息处理系统，信息处理装置和程序的控制方法
公开(公告)号：US20120254676A1
公开(公告)日：2012-10-04
申请号：US13416431
申请日：2012-03-09
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： H03M13/09 , G06F11/10 , G06F11/00
CPC分类号： G06F11/1008 , G01R31/3171 , G01R31/31816 , G06F1/324 , G06F1/3296 , G06F11/076 , H03M13/09 , H04L1/203 , Y02D10/126 , Y02D10/172
摘要： An information processing apparatus includes a first parity production section for producing a first error detection code for detecting an error of data. A second parity production section produces a second error detection code for detecting an error of the data from the first error detection code. A first parity checking section detects an error of the retained data as a first error using the retained first error detection code. A second parity checking section detects an error of the retained data as a second error using the retained second error detection code. A control amount outputting section outputs, when an occurrence rate of a first error is equal to or lower than a first threshold value, a control amount for controlling a power supply voltage or a frequency using a second threshold value as a target value for an occurrence rate of a second error.
摘要翻译：信息处理设备包括：第一奇偶校验生成部分，用于产生用于检测数据错误的第一错误检测码。第二奇偶校验生成部分产生用于检测来自第一错误检测码的数据的错误的第二错误检测码。第一奇偶校验部分使用保留的第一错误检测码来检测保留数据的错误作为第一错误。第二奇偶校验部分使用保留的第二错误检测码来检测作为第二错误的保留数据的错误。当第一误差的出现率等于或低于第一阈值时，控制量输出部分输出用于使用第二阈值控制电源电压或频率的控制量作为发生的目标值率的第二个错误。

19. 发明申请

US20120194246A1 DELAY LATCH CIRCUIT AND DELAY FLIP-FLOP 有权
标题翻译：延时锁定电路和延时片
公开(公告)号：US20120194246A1
公开(公告)日：2012-08-02
申请号：US13323378
申请日：2011-12-12
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： H03K3/037
CPC分类号： G11C19/00 , H03K3/037 , H03K3/0375 , H03K3/35625
摘要： Disclosed herein are a delay latch circuit and a delay flip-flop circuit arranged to inhibit the increase in power consumption while preventing malfunction under low voltage conditions. An internal signal output circuit outputs as an internal signal an inverted signal of a data signal starting from an internal transparency start timing until an internal transparency end timing. From the internal transparency end timing until the internal transparency start timing, the internal signal output circuit outputs a fixed value signal as the internal signal. A transistor delays the output internal signal over a time period which ranges from a hold instruction delay timing to the issuance of a data transparency instruction and which includes the internal transparency end timing therebetween.
摘要翻译：这里公开了延迟锁存电路和延迟触发器电路，其布置成在防止低电压条件下的故障的同时抑制功耗的增加。内部信号输出电路作为内部信号输出从内部透明度开始定时开始到内部透明度结束定时的数据信号的反相信号。从内部透明度结束定时到内部透明度开始定时，内部信号输出电路输出固定值信号作为内部信号。晶体管在从保持指令延迟定时到发出数据透明度指令的时间段内延迟输出内部信号，并且其包括其间的内部透明度结束定时。

20. 发明授权

US07840629B2 Methods and apparatus for providing a booth multiplier 失效
标题翻译：提供展位乘数的方法和装置
公开(公告)号：US07840629B2
公开(公告)日：2010-11-23
申请号：US11509492
申请日：2006-08-24
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F7/52 , G06F7/38
CPC分类号： G06F7/5332 , G06F7/5338
摘要： Methods and apparatus for converting a radix 2 multiplier to respective groups of radix 4 encoded bits representing numbers of the group consisting of −2, −1, 0, 1, 2, wherein the set of encoded bits includes: a first bit that is true when the associated number is 2, a second bit that is true when the associated number is −2, a third bit that is true when the associated number is either negative or zero, and a fourth bit that is true when the associated number has an absolute value of 1.
摘要翻译：用于将基数2乘法器转换成表示由-2，-1,0,1,2组成的组的编号的基数4编码比特的组的方法和装置，其中编码比特组包括：第一比特，其为真当相关联的号码为2时，当相关号码为-2时为第二位，当相关号码为负号或零时为真的第三位，当关联号码为绝对值1。

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