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11. 发明授权

US06844225B2 Self-aligned mask formed utilizing differential oxidation rates of materials 失效
标题翻译：使用材料的不同氧化速率形成的自对准掩模
公开(公告)号：US06844225B2
公开(公告)日：2005-01-18
申请号：US10345469
申请日：2003-01-15
申请人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
发明人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
IPC分类号： H01L21/321 , H01L21/331 , H01L29/732 , H01L29/737 , H01L21/00
CPC分类号： H01L29/66242 , H01L21/32105 , Y10S438/911
摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.
摘要翻译：使用不同材料的不同氧化速率形成自对准氧化物掩模。自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在多晶硅（或Si / siGe）。然后在自对准掩模形成之后形成隆起的外在基体。该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

12. 发明授权

US08405186B2 Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure 有权
标题翻译：具有侧壁限定的内在基极到外部基极连接区域的晶体管结构和形成该结构的方法
公开(公告)号：US08405186B2
公开(公告)日：2013-03-26
申请号：US12817249
申请日：2010-06-17
申请人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
IPC分类号： H01L21/70
CPC分类号： H01L29/732 , H01L29/66242 , H01L29/66287 , H01L29/7378
摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.
摘要翻译：公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度发射极层）进行选择性调整，以优化晶体管性能。

13. 发明授权

US07888745B2 Bipolar transistor with dual shallow trench isolation and low base resistance 有权
标题翻译：具有双浅沟槽隔离和低基极电阻的双极晶体管
公开(公告)号：US07888745B2
公开(公告)日：2011-02-15
申请号：US11425550
申请日：2006-06-21
申请人： Marwan H. Khater , Andreas D. Stricker , Bradley A. Orner , Mattias E. Dahlstrom
发明人： Marwan H. Khater , Andreas D. Stricker , Bradley A. Orner , Mattias E. Dahlstrom
IPC分类号： H01L29/72
CPC分类号： H01L29/7378 , H01L29/66242
摘要： An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair of neighboring first STI regions defines an active area in the substrate. The structure also includes a collector disposed in the in the active area of the semiconductor substrate, a base layer disposed atop a surface of the semiconductor substrate in the active area, and a raised extrinsic base disposed on the base layer. In accordance with the present, the raised extrinsic base has an opening to a portion of the base layer. An emitter is located in the opening and extending on a portion of the patterned raised extrinsic base; the emitter is spaced apart and isolated from the raised extrinsic base. Moreover, and in addition to the first STI region, a second shallow trench isolation (STI) region is present in the semiconductor substrate which extends inward from each pair of said first shallow trench isolation regions towards said collector. The second STI region has an inner sidewall surface that is sloped. In some embodiments, the base is completely monocrystalline.
摘要翻译：提供了具有双浅沟槽隔离的改进的双极晶体管，用于减小基极与集电极电容Ccb和基极电阻Rb的寄生分量。该结构包括具有设置在其中的至少一对相邻的第一浅沟槽隔离（STI）区域的半导体衬底。该对相邻的第一STI区域限定衬底中的有源区域。该结构还包括设置在半导体衬底的有源区域中的集电体，设置在有源区域中的半导体衬底的表面上的基极层和设置在基极层上的凸起的非本征基极。根据本发明，凸起的外在基部具有对基底层的一部分的开口。发射器位于开口中并在图案化的凸起的外基极的一部分上延伸; 发射极间隔开并与凸起的外基极隔离。而且，除了第一STI区之外，第二浅沟槽隔离（STI）区域存在于从每对所述第一浅沟槽隔离区向内朝向所述集电极延伸的半导体衬底中。第二STI区域具有倾斜的内侧壁表面。在一些实施方案中，碱是完全单晶的。

14. 发明申请

US20080268604A1 METHODS OF BASE FORMATION IN A BiCMOS PROCESS 失效
标题翻译： BiCMOS工艺中基质形成的方法
公开(公告)号：US20080268604A1
公开(公告)日：2008-10-30
申请号：US12128077
申请日：2008-05-28
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

15. 发明授权

US07442595B2 Bipolar transistor with collector having an epitaxial Si:C region 失效
标题翻译：具有集电极的双极晶体管具有外延Si：C区域
公开(公告)号：US07442595B2
公开(公告)日：2008-10-28
申请号：US11511047
申请日：2006-08-28
申请人： Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg , Andreas D. Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg , Andreas D. Stricker
IPC分类号： H01L21/337
CPC分类号： H01L29/66068 , H01L29/2003 , H01L29/66242
摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.
摘要翻译：提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

16. 发明授权

US07288827B2 Self-aligned mask formed utilizing differential oxidation rates of materials 有权
标题翻译：使用材料的不同氧化速率形成的自对准掩模
公开(公告)号：US07288827B2
公开(公告)日：2007-10-30
申请号：US10969718
申请日：2004-10-20
申请人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
发明人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
IPC分类号： H01L27/082 , H01L27/102
CPC分类号： H01L29/66242 , H01L21/32105 , Y10S438/911
摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.
摘要翻译：使用不同材料的不同氧化速率形成自对准氧化物掩模。自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在多晶硅（或Si / siGe）。然后在自对准掩模形成之后形成隆起的外在基体。该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

17. 发明授权

US07696034B2 Methods of base formation in a BiCOMS process 失效
标题翻译： BiCOMS工艺中碱形成的方法
公开(公告)号：US07696034B2
公开(公告)日：2010-04-13
申请号：US12128077
申请日：2008-05-28
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , Beth Ann Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , Beth Ann Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/8238
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

18. 发明授权

US07253096B2 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 失效
标题翻译：双极晶体管具有可选择的自对准的外部基极和其形成方法
公开(公告)号：US07253096B2
公开(公告)日：2007-08-07
申请号：US11289915
申请日：2005-11-30
申请人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
发明人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
IPC分类号： H01L21/4763
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.
摘要翻译：公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。然后通过在第一非本征基层上的光刻形成电介质着色焊盘。接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

19. 发明授权

US07136268B2 Tunable ESD trigger and power clamp circuit 失效
标题翻译：可调谐ESD触发和电源钳位电路
公开(公告)号：US07136268B2
公开(公告)日：2006-11-14
申请号：US10708911
申请日：2004-03-31
申请人： Andreas D. Stricker , Steven H. Voldman
发明人： Andreas D. Stricker , Steven H. Voldman
IPC分类号： H02H9/00 , H01L23/62
CPC分类号： H01L27/0259 , H01L29/7378 , H01L2924/0002 , H01L2924/00
摘要： A circuit and a method for the electrostatic discharge protection of integrated circuits. The electrostatic discharge protection circuit, including: an electrostatic discharge protection circuit, comprising: a first bipolar transistor coupled between a first circuit node and a second circuit node, the first bipolar transistor having a non-uniform subcollector region geometry, the first bipolar transistor having a different value for collector to emitter breakdown voltage than a value for collector to emitter breakdown voltage of an otherwise identical bipolar transistor having a uniform subcollector region geometry.
摘要翻译：集成电路的静电放电保护电路及方法。该静电放电保护电路包括：静电放电保护电路，包括：耦合在第一电路节点和第二电路节点之间的第一双极晶体管，所述第一双极晶体管具有不均匀的子集电极区域几何形状，所述第一双极晶体管具有相对于具有均匀子集电极区域几何形状的相同的双极晶体管的集电极至发射极击穿电压的值，集电极至发射极击穿电压的值不同。

20. 发明授权

US06906401B2 Method to fabricate high-performance NPN transistors in a BiCMOS process 有权
标题翻译：在BiCMOS工艺中制造高性能NPN晶体管的方法
公开(公告)号：US06906401B2
公开(公告)日：2005-06-14
申请号：US10856503
申请日：2004-05-28
申请人： James S. Dunn , Natalie B. Feilchenfeld , Qizhi Liu , Andreas D. Stricker
发明人： James S. Dunn , Natalie B. Feilchenfeld , Qizhi Liu , Andreas D. Stricker
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/737 , H01L29/72
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/7378
摘要： A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.
摘要翻译：提供了一种形成表现出高性能的准自对准异质结双极晶体管（HBT）的方法。该方法包括使用图案化的发射器着陆焊盘叠层，其用于改进发射极开口光刻的对准以及用于发射极开口蚀刻的蚀刻停止层。本发明还提供了一种HBT，其包括具有位于发射器着陆焊盘堆叠下方的单晶区域的凸起的外部基极。

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