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11. 发明授权

US08027657B2 Sampling mixer with asynchronous clock and signal domains 有权
标题翻译：具有异步时钟和信号域的采样混频器
公开(公告)号：US08027657B2
公开(公告)日：2011-09-27
申请号：US10121761
申请日：2002-04-12
申请人： Robert B. Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
IPC分类号： H04B1/26 , H04L27/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译：具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。利用混频器中不同采样电容器之间的显着电容差和叠加特性。

12. 发明授权

US07411444B2 Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权
标题翻译：使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术
公开(公告)号：US07411444B2
公开(公告)日：2008-08-12
申请号：US10712593
申请日：2003-11-13
申请人： Khurram Muhammad , Robert B. Staszewski , Dirk Leipold
发明人： Khurram Muhammad , Robert B. Staszewski , Dirk Leipold
IPC分类号： H03K5/00
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译：改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。

13. 发明授权

US07057540B2 Sigma-delta (ΣΔ) analog-to-digital converter (ADC) structure incorporating a direct sampling mixer 有权
标题翻译：结合直接采样混频器的Sigma-delta（SigmaDelta）模数转换器（ADC）结构
公开(公告)号：US07057540B2
公开(公告)日：2006-06-06
申请号：US10273217
申请日：2002-10-17
申请人： Khurram Muhammad , Robert B. Staszewski , Feng Chen , Dirk Leipold
发明人： Khurram Muhammad , Robert B. Staszewski , Feng Chen , Dirk Leipold
IPC分类号： H03M3/00
CPC分类号： H03M3/47 , H03M3/496 , H04B1/1036
摘要： A sigma-delta analog-to-digital converter-offers advantages such as noise shaping and high frequency operation. However, a sampling circuit needed to provide a highly oversampled discrete-time sample stream with low noise characteristics is difficult to design and implement. The present invention provides a sigma-delta mixer 300 with such a sampling circuit 310. The present invention discloses a sampling circuit using switched capacitors 307, 308, and 309 with low noise characteristics and at the same time is capable of providing a highly oversampled discrete-time sample stream.
摘要翻译： Σ-Δ模数转换器 - 具有噪声整形和高频操作等优点。然而，需要提供具有低噪声特性的高度过采样离散时间采样流所需的采样电路难以设计和实现。本发明提供了具有这种采样电路310的Σ-Δ混合器300。本发明公开了一种使用具有低噪声特性的开关电容器307,308和309的采样电路，同时能够提供高度过采样的离散时间采样流。

14. 发明授权

US07006813B2 Efficient charge transfer using a switched capacitor resistor 有权
公开(公告)号：US07006813B2
公开(公告)日：2006-02-28
申请号：US10147784
申请日：2002-05-16
申请人： Robert B. Staszewski , Khurram Muhammad , Chih-Ming Hung , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Chih-Ming Hung , Dirk Leipold
IPC分类号： H04B1/26
CPC分类号： H03D7/125 , H04B1/1036
摘要： The application of a non-zero voltage offset to rotating capacitors 1111 and 1112 permit the use of a single positive voltage supply. However, the precharging of the rotating capacitors 1111 and 1112 is power inefficient. A power efficient and low-noise precharging operation is realized through the sharing of the charge on a feedback capacitor 1075 and 1080 that is significantly larger than the rotating capacitors 1111. Once a precharging operation is complete, the charge on the feedback capacitor 1075 and 1080 is refreshed from its residual charge level (rather than zero charge level) to a desired charge level.

15. 发明申请

US20090196384A1 Direct Radio Frequency (RF) Sampling With Recursive Filtering Method 审中-公开
标题翻译：直接射频（RF）采样递归滤波方法
公开(公告)号：US20090196384A1
公开(公告)日：2009-08-06
申请号：US12334268
申请日：2008-12-12
申请人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
IPC分类号： H03D1/04
CPC分类号： H03D7/125 , H04B1/1036
摘要： A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).
摘要翻译：具有采样混合器1100的无线电接收机2000，用于通过用历史和旋转电容器1111和1112直接采样RF电流来产生离散时间采样流，其中读出旋转电容器上的累积电荷以产生样本。混合器通过预测毛刺的发生（或检测观察到的和预测的样品之间的显着差异）并为损坏的样品产生校正的样品来提供对噪声毛刺的免疫。这些校正样本可以用专用电路1933（数字）或混合器1100（模拟）来创建。

16. 发明授权

US07463873B2 Wireless communications device having type-II all-digital phase-locked loop (PLL) 有权
标题翻译：具有II型全数字锁相环（PLL）的无线通信设备
公开(公告)号：US07463873B2
公开(公告)日：2008-12-09
申请号：US11122670
申请日：2005-05-04
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03L7/093
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115 ) and an integral loop gain block (integral loop gain block 1120 ). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the intergral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译：用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

17. 发明授权

US06791422B2 Frequency synthesizer with digitally-controlled oscillator 有权
标题翻译：具有数字控制振荡器的频率合成器
公开(公告)号：US06791422B2
公开(公告)日：2004-09-14
申请号：US10679792
申请日：2003-10-06
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
IPC分类号： H03L700
CPC分类号： H03C3/0975 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0966 , H03K19/0016 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/50 , H04L7/0029
摘要： A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.
摘要翻译：基于频率合成器的发射机（10）包括具有各种电容器阵列的数字控制振荡器（DCO）的LC箱（12）。液相色谱箱12分为反映两种一般操作模式的两个主要组：采集和跟踪。第一组（过程/电压/温度和采集）最初初始化设置所需的中心振荡频率，而第二组（整数和分数跟踪）在实际操作期间精确地控制振荡频率。对于高精度输出，在整数跟踪控制器中使用动态元件匹配（DEM）来减少由非均匀电容值引起的非线性。此外，在获取所选择的信道之后，整数跟踪电容器阵列的优选范围可以用于调制。数字Σ-Δ调制器电路（50）响应错误字的分数位驱动电容器阵列（14d）。在模式开关上，累加误差被重新计算到相位重启值，以防止扰动。

18. 发明授权

US08542616B2 Simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing 有权
标题翻译：使用频率复用和共享处理的同时多信号接收和传输
公开(公告)号：US08542616B2
公开(公告)日：2013-09-24
申请号：US12250646
申请日：2008-10-14
申请人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
IPC分类号： H04L5/14
CPC分类号： H04B1/0075 , H03D7/1441 , H03D7/1466 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03D2200/0047 , H03D2200/0074 , H03D2200/0084 , H03D2200/0088 , H04L5/06 , H04L5/143 , H04L27/3863 , H04L2027/0016
摘要： A novel mechanism for simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing. Multiple RF signals, which may be of various wireless standards, are received using one or more shared processing blocks thereby significantly reducing chip space and power requirements. Shared components include local oscillators, analog to digital converters, digital RX processing and digital baseband processing. In operation, multiple RX front end circuits, one for each desired wireless signal, generate a plurality of IF signals that are frequency multiplexed and combined to create a single combined IF signal. The combined IF signal is processed by a shared processing block. Digital baseband processing is performed on each receive signal to generate respective data outputs. Further, simultaneous full-duplex transmission and reception is performed using a single local oscillator. The phase/frequency modulation of the frequency synthesizer used in the TX is removed from the local oscillator signal for use in the receiver.
摘要翻译：一种使用频率复用和共享处理同时进行多信号接收和传输的新颖机制。可以使用一个或多个共享处理块来接收可能具有各种无线标准的多个RF信号，从而显着减少芯片空间和功率需求。共享组件包括本地振荡器，模数转换器，数字RX处理和数字基带处理。在操作中，针对每个期望的无线信号的多个RX前端电路产生频率多路复用并组合以产生单个组合IF信号的多个IF信号。组合的IF信号由共享处理块处理。对每个接收信号执行数字基带处理，以产生相应的数据输出。此外，使用单个本地振荡器执行同时的全双工发送和接收。在TX中使用的频率合成器的相位/频率调制从本地振荡器信号中去除，以在接收机中使用。

19. 发明授权

US08306176B2 Fine-grained gear-shifting of a digital phase-locked loop (PLL) 有权
标题翻译：数字锁相环（PLL）的细粒度换档
公开(公告)号：US08306176B2
公开(公告)日：2012-11-06
申请号：US10464982
申请日：2003-06-19
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03D3/24
CPC分类号： H03L7/107 , H03L7/087 , H03L7/093 , H03L2207/50
摘要： System and method for improving a digital PLL's performance by making fine grained adjustments to the loop gain. A preferred embodiment comprises a plurality of loop gain adjustors (such as loop gain adjustors 605, 606, 607, and 608) that can incrementally adjust the loop gain. The incrementally adjusted loop gains are sequentially brought on-line so that the loop gain of the digital PLL is slowly decreased. By slowly decreasing the loop gain, the digital PLL is less perturbed by smaller noise transients that would take time to settle. Hence, the digital PLL can quickly acquire a signal and then decrease its loop gain and hence its bandwidth when it only needs to track a signal. The reduced bandwidth also reduces the overall noise in the digital PLL that is due to the reference noise contribution.
摘要翻译：通过对环路增益进行细微调整来提高数字PLL性能的系统和方法。优选实施例包括可逐渐调节环路增益的多个环路增益调节器（例如环路增益调节器605,606,607和608）。递增调节的环路增益被顺序地串联在一起，使得数字PLL的环路增益缓慢降低。通过缓慢地减小环路增益，数字PLL不受较小的噪声瞬变扰动，这将需要一些时间来解决。因此，数字PLL可以快速获取信号，然后在仅需要跟踪信号时减小其环路增益，从而降低其带宽。降低的带宽也降低了由于参考噪声贡献而导致的数字PLL中的整体噪声。

20. 发明授权

US08000670B2 Removing close-in interferers through a feedback loop 有权
标题翻译：通过反馈回路消除紧密的干扰源
公开(公告)号：US08000670B2
公开(公告)日：2011-08-16
申请号：US11339386
申请日：2006-01-25
申请人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
IPC分类号： H04B1/06
CPC分类号： H04B1/28 , H04B1/1036
摘要： System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.
摘要翻译：通过反馈消除接近干扰的系统和方法。优选实施例包括耦合到直接RF无线电接收机（例如，无线电接收机800）的数字输出的干扰源预测器（例如，干扰源预测器840）。干扰源预测器预测干扰源的存在，并且通过使用电荷共享通过反馈电路（例如，反馈单元845）将信息反馈给采样单元（例如，采样单元805）。然后在采样单元中消除干扰源。另外，通过执行任意系数有限脉冲响应滤波器来增加和改变采样单元滤波器中的零数和位置。

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