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11. 发明授权

US08358011B1 Interconnect structures with engineered dielectrics with nanocolumnar porosity 失效
标题翻译：互连结构与具有纳米柱孔隙度的工程电介质
公开(公告)号：US08358011B1
公开(公告)日：2013-01-22
申请号：US11899842
申请日：2007-09-07
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/48
CPC分类号： H01L23/53295 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

12. 发明申请

US20130009315A1 INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY 失效
标题翻译：具有纳米孔隙度的工程电介质的互连结构
公开(公告)号：US20130009315A1
公开(公告)日：2013-01-10
申请号：US11899842
申请日：2007-09-07
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

13. 发明申请

US20080096330A1 HIGH-PERFORMANCE CMOS SOI DEVICES ON HYBRID CRYSTAL-ORIENTED SUBSTRATES 失效
标题翻译：高性能CMOS SOI器件在混合晶体导向衬底上的应用
公开(公告)号：US20080096330A1
公开(公告)日：2008-04-24
申请号：US11958877
申请日：2007-12-18
申请人： Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey Sleight , Min Yang
发明人： Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey Sleight , Min Yang
IPC分类号： H01L21/84
CPC分类号： H01L21/76275 , H01L21/823807 , H01L21/84
摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
摘要翻译：提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

14. 发明申请

US20080042140A1 THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN 审中-公开
标题翻译：三维集成电路和设计方法
公开(公告)号：US20080042140A1
公开(公告)日：2008-02-21
申请号：US11847608
申请日：2007-08-30
申请人： Syed Alam , Ibrahim Elfadel , Kathryn Guarini , Meikei Ieong , Prabhakar Kudva , David Kung , Mark Lavin , Arifur Rahman
发明人： Syed Alam , Ibrahim Elfadel , Kathryn Guarini , Meikei Ieong , Prabhakar Kudva , David Kung , Mark Lavin , Arifur Rahman
IPC分类号： H01L29/04
CPC分类号： H01L27/0688 , H01L21/2007 , H01L21/84 , H01L27/1203
摘要： A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.
摘要翻译：三维（3D）集成电路（IC），3D IC芯片和3D IC芯片的制造方法。该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。

15. 发明申请

US20050067620A1 Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers 审中-公开
标题翻译：三维CMOS集成电路具有建立在不同晶体取向晶片上的器件层
公开(公告)号：US20050067620A1
公开(公告)日：2005-03-31
申请号：US10914433
申请日：2004-08-09
申请人： Victor Chan , Kathryn Guarini , Meikei Ieong
发明人： Victor Chan , Kathryn Guarini , Meikei Ieong
IPC分类号： H01L27/08 , H01L21/02 , H01L21/336 , H01L21/68 , H01L21/8238 , H01L23/52 , H01L27/00 , H01L27/06 , H01L27/085 , H01L27/092 , H01L27/12 , H01L29/786 , H01L29/76 , H01L21/84
CPC分类号： H01L21/6835 , H01L25/0657 , H01L27/0688 , H01L27/1203 , H01L2221/68368 , H01L2924/0002 , H01L2924/00
摘要： Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias. In a second 3D integration scheme, a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation is bonded to a surface of a pre-fabricating wafer having second semiconductor devices on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and forming first semiconductor device on the first SOI layer.
摘要翻译：提供制造3D集成电路的三维（3D）积分方案，其中pFET位于该器件的最佳晶体表面上，并且nFET位于用于该类型器件的最佳晶体表面上。根据本发明的第一3D集成方案，第一半导体器件预先构建在第一绝缘体上硅（SOI）衬底的半导体表面上，并且第二半导体器件预先构建在第一绝缘体上硅绝缘体第二SOI衬底。在预先构建这两个结构之后，将结构粘合在一起并通过晶片通孔通孔进行互连。在第二3D集成方案中，具有第一晶体取向的第一SOI层的绝缘硅绝缘体（SOI）衬底被结合到具有第二SOI层的具有第二半导体器件的预制晶片的表面上，所述第二SOI层具有不同于第一SOI层的晶体取向; 以及在所述第一SOI层上形成第一半导体器件。

16. 发明申请

US20050056937A1 Connection device and method of forming a connection device 失效
标题翻译：连接装置及形成连接装置的方法
公开(公告)号：US20050056937A1
公开(公告)日：2005-03-17
申请号：US10662709
申请日：2003-09-15
申请人： David Frank , Kathryn Guarini , Christopher Murray , Xinlin Wang , Hon-Sum Wong
发明人： David Frank , Kathryn Guarini , Christopher Murray , Xinlin Wang , Hon-Sum Wong
IPC分类号： H01L23/522 , H01L23/525 , H01L23/48
CPC分类号： H01L23/525 , H01L23/5226 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.
摘要翻译：连接装置包括将第一金属层连接到第二金属层的多个可重新配置的通孔。致动元件设置在第一金属层和第二金属层之间。致动元件改变多个可重新配置的通孔的配置，以改变导电状态和非导通状态之间的多个可重新配置的通孔。

17. 发明授权

US08901741B2 Interconnect structures with engineered dielectrics with nanocolumnar porosity 有权
标题翻译：互连结构与具有纳米柱孔隙度的工程电介质
公开(公告)号：US08901741B2
公开(公告)日：2014-12-02
申请号：US13531518
申请日：2012-06-23
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/522 , H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

18. 发明申请

US20070287224A1 THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN 失效
标题翻译：三维集成电路和设计方法
公开(公告)号：US20070287224A1
公开(公告)日：2007-12-13
申请号：US11737598
申请日：2007-04-19
申请人： Syed Alam , Ibrahim Elfadel , Kathryn Guarini , Meikei Ieong , Prabhakar Kudva , David Kung , Mark Lavin , Arifur Rahman
发明人： Syed Alam , Ibrahim Elfadel , Kathryn Guarini , Meikei Ieong , Prabhakar Kudva , David Kung , Mark Lavin , Arifur Rahman
IPC分类号： H01L21/02
CPC分类号： H01L27/0688 , H01L21/2007 , H01L21/84 , H01L27/1203
摘要： A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.
摘要翻译：三维（3D）集成电路（IC），3D IC芯片和制造3D IC芯片的方法。该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。

19. 发明申请

US20070218621A1 Integration of strained Ge into advanced CMOS technology 有权
标题翻译：将应变锗融入先进的CMOS技术
公开(公告)号：US20070218621A1
公开(公告)日：2007-09-20
申请号：US11799261
申请日：2007-04-10
申请人： Huiling Shang , Meikei Leong , Jack Chu , Kathryn Guarini
发明人： Huiling Shang , Meikei Leong , Jack Chu , Kathryn Guarini
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/7841
摘要： A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.
摘要翻译：公开了一种用于压缩应变Ge层中的PFET器件的结构和方法。这种器件的制造方法与标准CMOS技术兼容，并且具有完全可扩展性。该处理包括超过50％Ge含量缓冲层，纯Ge层和SiGe顶层的选择性外延沉积。承载在压缩应变Ge层中的制造掩埋沟道PMOS器件相对于类似的Si器件显示出优异的器件特性。

20. 发明申请

US20060163646A1 Nonvolatile memory device using semiconductor nanocrystals and method of forming same 有权
公开(公告)号：US20060163646A1
公开(公告)日：2006-07-27
申请号：US11373127
申请日：2006-03-13
申请人： Charles Black , Kathryn Guarini
发明人： Charles Black , Kathryn Guarini
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , B82Y10/00 , G11C2216/06 , H01L21/02118 , H01L21/02227 , H01L21/02532 , H01L21/02636 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L29/42332 , H01L29/7887 , H01L29/7923 , Y10S438/947 , Y10S977/78 , Y10S977/783 , Y10S977/813 , Y10S977/856 , Y10S977/883 , Y10S977/888 , Y10S977/893
摘要： A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.

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