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11. 发明申请

US20050286891A1 Optical-switch testing apparatus, optical-signal switching apparatus, optical-switch testing method, and control method for optical-signal switching 有权
标题翻译：光开关测试装置，光信号开关装置，光开关测试方法以及光信号切换控制方法
公开(公告)号：US20050286891A1
公开(公告)日：2005-12-29
申请号：US10876645
申请日：2004-06-28
申请人： Yoshio Sakai , Yuji Tochio , Kazuyuki Mori , Atsuo Ishizuka
发明人： Yoshio Sakai , Yuji Tochio , Kazuyuki Mori , Atsuo Ishizuka
IPC分类号： G02B6/35 , H04J14/00 , H04Q11/00
CPC分类号： G02B6/3586 , G02B6/3512 , G02B6/3556 , G02B6/356 , G02B6/3588 , H04Q11/0005 , H04Q2011/0049
摘要： A light source supplies optical signal to an optical switch and a detector detects light receiving level. A control unit changes a deflection control amount for changing an angle of a tilt mirror, and outputs the deflection control amount to a driving unit. When an input and an output ports are same, optical offset of the tilt mirror is calculated based on optimal angle at which the light detector detects an optimal point of the light receiving level. Whenever the input and the output port are different, a structure parameter of the tilt mirror is calculated based on the optical offset and the optimal angle. The optical offset and the structure parameter are stored in a memory as a test result.
摘要翻译：光源将光信号提供给光开关，检测器检测光接收电平。控制单元改变用于改变倾斜镜的角度的偏转控制量，并将偏转控制量输出到驱动单元。当输入端口和输出端口相同时，基于光检测器检测到光接收电平的最佳点的最佳角度来计算倾斜镜的光学偏移。无论何时输入和输出端口不同，基于光学偏移和最佳角度计算倾斜镜的结构参数。光学偏移和结构参数作为测试结果存储在存储器中。

12. 发明申请

US20050213178A1 Controlling apparatus and controlling method for spatial optical switch 审中-公开
标题翻译：空间光开关控制装置及控制方法
公开(公告)号：US20050213178A1
公开(公告)日：2005-09-29
申请号：US10893320
申请日：2004-07-19
申请人： Yoshio Sakai , Kazuyuki Mori
发明人： Yoshio Sakai , Kazuyuki Mori
IPC分类号： G02B26/08 , G02B6/28 , G02B6/35 , H04B10/07 , H04B10/27 , H04B10/29 , H04J14/00 , H04J14/02
CPC分类号： G02B6/3588 , G02B6/3512 , G02B6/3556 , G02B6/356
摘要： A controlling apparatus for a spatial optical switch having a deflecting means which has two or more deflection axes, and controls deflection angles around deflection axes to deflect an optical path of an input light beam from any one of a plurality of input ports, and outputs the input light beam to any one of a plurality of output ports. The controlling apparatus comprises an optical detecting means for detecting an output optical level from the output port in order to control the output optical level of the spatial optical switch at a high resolution, and a controlling means for controlling the output optical level detected by the optical detecting means to a desired output optical level by controlling a deflection angle around one deflection axis of the deflection means, then controlling a deflection angle about another deflection axis of the deflecting means.
摘要翻译：一种用于空间光开关的控制装置，具有偏转装置，该偏转装置具有两个或更多个偏转轴，并且控制偏转轴周围的偏转角以偏转来自多个输入端口中的任何一个的输入光束的光路，并输出将光束输入到多个输出端口中的任何一个。控制装置包括一个光学检测装置，用于检测来自输出端口的输出光学电平，以便以高分辨率控制空间光学开关的输出光学电平;以及控制装置，用于控制由光学器件检测到的输出光学电平通过控制偏转装置的一个偏转轴周围的偏转角来控制所需输出光学水平的检测装置，然后控制偏转装置的另一个偏转轴的偏转角。

13. 发明申请

US20050035569A1 Hand-driven vehicle 失效
标题翻译：手动车
公开(公告)号：US20050035569A1
公开(公告)日：2005-02-17
申请号：US10942255
申请日：2004-09-15
申请人： Shigeru Ikeda , Shoji Ohshita , Yoshio Sakai
发明人： Shigeru Ikeda , Shoji Ohshita , Yoshio Sakai
IPC分类号： B62K5/04 , B62M1/16 , B62M1/14
CPC分类号： B62M1/16
摘要： A vehicle body is provided with a rear wheel at a rear portion, and a front wheel coupled to a handle post. A swing-enabling shaft is rotatably provided on the upper portion of the handle post. A handlebars unit is attached to the swing-enabling shaft such that it can swing forward and backward relative to the vehicle body. When the handlebars unit is swung, a driving mechanism is driven. The driving mechanism rotates the front wheel such that the vehicle body advances, regardless of whether the handlebars unit is swung forward or backward.
摘要翻译：车体在后部设置有后轮，以及联接到手柄柱的前轮。可旋转地设置在手柄柱的上部的摆动轴。把手单元连接到可摆动轴上，使得其可相对于车身前后摆动。当把手单元摆动时，驱动机构被驱动。驱动机构使前轮旋转，使得车身前进，而不管车把单元是向前还是向后摆动。

14. 发明授权

US5772602A Noninvasive blood pressure measuring device and method 失效
标题翻译：无创血压测量装置及方法
公开(公告)号：US5772602A
公开(公告)日：1998-06-30
申请号：US747896
申请日：1996-11-13
申请人： Yoshio Sakai , Toshichika Kaji
发明人： Yoshio Sakai , Toshichika Kaji
IPC分类号： A61B5/022 , A61B5/025
CPC分类号： A61B5/025 , A61B5/022
摘要： A CPU 9 controls an air supplying/discharging device to set a pressure of air within a-cuff to 60 mmHg for 60 seconds before making a blood pressure measurement, detects pulse waves of the cuff pressure for such period of time, and calculates a degree of stability of the detected pulse waves. When a blood pressure measurement is made, the CPU reduces the cuff pressure by a step pressure reducing operation whose step duration corresponds to the calculated degree of stability.
摘要翻译：在进行血压测量之前，CPU9控制空气供给/排出装置，将袖带内的空气压力设定为60mmHg，持续60秒钟，检测袖带压力的脉搏波在这样的时间段内，检测到的脉搏波的稳定性。当进行血压测量时，CPU通过步进压力降低操作来减小袖带压力，其阶梯持续时间对应于计算出的稳定度。

15. 发明授权

US5584299A Heart pulse wave detecting device using iterative base point detection 失效
标题翻译：心脏脉搏波检测装置采用迭代基点检测
公开(公告)号：US5584299A
公开(公告)日：1996-12-17
申请号：US507142
申请日：1995-07-26
申请人： Yoshio Sakai , Jun Motogi , Sunao Takeda
发明人： Yoshio Sakai , Jun Motogi , Sunao Takeda
IPC分类号： A61B5/022 , A61B5/021
CPC分类号： A61B5/6826 , A61B5/022 , A61B5/6838 , A61B5/7239 , A61B5/6824
摘要： A CPU of a control unit receives a blood pressure pulse wave signal, through an AC amplifier and an A/D convertor. The CPU differentiates, for the smoothing of the waveform, the heart pulse wave signal every step of decreasing the pressure in the cuff, thereby detecting a descending zero-cross point m of the differential wave. Further, the CPU detects a slope peak point P' while tracing back from the descending zero-cross point m. The CPU determines the peak points of the pulse wave by using the heart pulse wave signal that is not differentiated. Thereafter, the CPU determines the base points of the pulse wave tracing back from the maximum-slope point, determines the peak value of the heart pulse wave signal in all the steps of decreasing the pressure in the cuff, and finally computes a systolic blood pressure and a diastolic blood pressure.
摘要翻译：控制单元的CPU通过AC放大器和A / D转换器接收血压脉搏波信号。为了平滑波形，CPU对每一步减小袖带压力的心搏波信号进行微分，从而检测差动波的下降零交叉点m。此外，CPU从下降的零交叉点m追溯回检测斜率峰值点P'。 CPU通过使用不区分的心脏脉搏波信号来确定脉搏波的峰值点。此后，CPU从最大斜坡点确定脉搏波跟踪的基点，在减小袖带压力的所有步骤中确定心脏脉搏波信号的峰值，并最终计算收缩压和舒张压。

16. 发明授权

US4797717A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4797717A
公开(公告)日：1989-01-10
申请号：US039291
申请日：1987-04-17
申请人： Koichiro Ishibashi , Osamu Minato , Toshiaki Masuhara , Yoshio Sakai , Toshiaki Yamanaka , Naotaka Hashimoto , Shoji Hanamura , Nobuyuki Moriwaki , Shigeru Honjyo , Kiyotsugu Ueda
发明人： Koichiro Ishibashi , Osamu Minato , Toshiaki Masuhara , Yoshio Sakai , Toshiaki Yamanaka , Naotaka Hashimoto , Shoji Hanamura , Nobuyuki Moriwaki , Shigeru Honjyo , Kiyotsugu Ueda
IPC分类号： G11C11/403 , H01L21/8234 , H01L21/8244 , H01L27/088 , H01L27/10 , H01L27/11 , H01L29/45 , H01L29/78 , H01L27/02 , H01L29/04
CPC分类号： H01L29/456 , H01L27/1112 , Y10S257/904
摘要： Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.
摘要翻译： SRAM中的每个存储单元包括两个驱动器MOS晶体管，两个传输门MOS晶体管和两个负载电阻。 MOS晶体管的栅极电极层由设置在半导体衬底的表面上的第一级导电层形成。每个存储单元中的两个驱动器MOS晶体管的源极区域共同连接，并且通过第二级导电层进一步连接到地电位点。每个存储单元中的两个负载电阻由第三级高电阻材料层形成。第二级导电层由低电阻材料层形成。因此，两个驱动器MOS晶体管的源极的电阻降低。

17. 发明授权

US4792841A Semiconductor devices and a process for producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US4792841A
公开(公告)日：1988-12-20
申请号：US634037
申请日：1984-07-24
申请人： Kouichi Nagasawa , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Satoshi Meguro
发明人： Kouichi Nagasawa , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Satoshi Meguro
IPC分类号： H01L29/78 , H01L21/285 , H01L21/768 , H01L21/8244 , H01L23/485 , H01L23/522 , H01L23/532 , H01L27/11 , H01L29/04
CPC分类号： H01L27/1112 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/522 , H01L23/53271 , H01L2924/0002 , Y10S257/903
摘要： Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.
摘要翻译：公开了包括多个硅栅型MOSFET的MOSIC，其中在与多晶硅栅极同时形成多晶硅布线之后，与源极和漏极区域接触的电极由多晶硅制成，以便连接到多晶硅从而防止源极和漏极区域的浅的pn结被触点破坏并提供与一个硅芯片的高度集成。

18. 发明授权

US4355374A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4355374A
公开(公告)日：1982-10-19
申请号：US172378
申请日：1980-07-24
申请人： Yoshio Sakai , Mitsumasa Koyanagi , Hideo Sunami , Norikazu Hashimoto
发明人： Yoshio Sakai , Mitsumasa Koyanagi , Hideo Sunami , Norikazu Hashimoto
IPC分类号： G11C11/401 , G11C11/404 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , G11C11/40 , G11C11/24
CPC分类号： G11C11/404 , H01L27/10805 , H01L27/10808
摘要： A semiconductor memory comprising a memory cell disposed on a p-type semiconductor substrate and including an insulated-gate field effect transistor and a storage capacitor. The storage capacitor comprises: an insulator capacitor including a first electrode disposed on the substrate, a film of Si.sub.3 N.sub.4 disposed on the first electrode, and a second electrode disposed on the Si.sub.3 N.sub.4 film; and a pn junction capacitor including a first n-type impurity region for constituting either the source or drain of the insulated-gate field effect transistor, and a second p-type impurity region disposed in contact with the first impurity region and having a higher impurity concentration than the substrate.
摘要翻译：一种半导体存储器，包括设置在p型半导体衬底上并包括绝缘栅场效应晶体管和存储电容器的存储单元。存储电容器包括：绝缘体电容器，包括设置在基板上的第一电极，设置在第一电极上的Si 3 N 4膜和设置在Si 3 N 4膜上的第二电极; 以及包含用于构成绝缘栅场效应晶体管的源极或漏极的第一n型杂质区和与第一杂质区接触并具有较高杂质的第二p型杂质区的pn结电容器浓度比底物。

19. 发明授权

US4031439A Over-speed preventing apparatus for DC motor 失效
标题翻译：直流电机超速防止装置
公开(公告)号：US4031439A
公开(公告)日：1977-06-21
申请号：US595365
申请日：1975-07-11
申请人： Yoshio Sakai , Toshiaki Kurosawa
发明人： Yoshio Sakai , Toshiaki Kurosawa
IPC分类号： B66B1/24 , B66B1/30 , B66B5/02 , B66B5/06 , H02P3/08 , H02P7/34 , H02P7/06
CPC分类号： B66B5/06 , B66B1/30 , H02P7/347 , Y10S388/902 , Y10S388/903 , Y10S388/917
摘要： An over-speed preventing apparatus for the DC motor comprises a DC motor the speed of which is controlled by the adjustment of the armature voltage thereof, controlled-rectifier means for supplying power to the separately excited field winding of the motor, means for generating a predetermined field current command, means for detecting the field current, and a constant current control system for controlling the rectifier means in accordance with the error between the field current command and the detected value of the field current. The apparatus further comprises a unidirectional element connected in parallel to the field winding in the direction in which the field current is made to flow back, current decrease detector means inserted between the rectifier circuit and the parallel circuit including the field winding and the unidirectional element, and protecting means energized by the current decrease detector means.
摘要翻译：用于直流电动机的超速防止装置包括直流电动机，其速度通过其电枢电压的调节来控制，用于向电动机的分别激励的励磁绕组供电的受控整流装置，预定励磁电流指令，用于检测励磁电流的装置;以及恒流控制系统，用于根据励磁电流指令与励磁电流的检测值之间的误差来控制整流装置。该装置还包括一个与励磁绕组并联连接的励磁电流使其流回的方向的单向元件，插入在整流电路和包括励磁绕组和单向元件的并联电路之间的电流减小检测装置，以及由电流降低检测器装置通电的保护装置。

20. 发明授权

US08331402B2 Optical transmission device, scrambling method, and descrambling method 有权
标题翻译：光传输设备，扰频方式和解扰方式
公开(公告)号：US08331402B2
公开(公告)日：2012-12-11
申请号：US12081220
申请日：2008-04-11
申请人： Yoshio Sakai , Kazuyuki Mori
发明人： Yoshio Sakai , Kazuyuki Mori
IPC分类号： H04J3/24
CPC分类号： H04J3/1694 , H04J3/1658 , H04Q11/0067 , H04Q2011/0086
摘要： A first header-attaching unit attaches to data of a low speed bit rate A, a header of the bit rate A. A second header-attaching unit attaches the header of the bit rate A to data of a high speed bit rate B. A combining unit combines outputs of the first and the second header-attaching units. A low speed scrambling unit performs a scrambling process on combined data by using a clock corresponding to the bit rate A. A high speed scrambling unit performs a scrambling process on the data of the bit rate B by using a clock corresponding to the bit rate B. During a timing corresponding to the bit rate A in the frame, a selector selects an output of the low speed scrambling unit. During a timing corresponding to the bit rate B in the frame, the selector selects an output of the high speed scrambling unit.
摘要翻译：第一标题附加单元附加到低速比特率A的数据，比特率A的标题。第二标题附加单元将比特率A的报头附加到高速比特率B的数据。组合单元组合第一和第二插头附接单元的输出。低速扰频单元通过使用对应于比特率A的时钟对组合数据进行加扰处理。高速扰频单元通过使用与比特率B相对应的时钟对比特率B的数据执行加扰处理在对应于帧中的比特率A的定时期间，选择器选择低速扰频单元的输出。在对应于帧中的比特率B的定时期间，选择器选择高速扰频单元的输出。

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