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11. 发明申请

US20050111602A1 Timing comparator, data sampling apparatus, and testing apparatus 失效
标题翻译：定时比较器，数据取样装置和检测装置
公开(公告)号：US20050111602A1
公开(公告)日：2005-05-26
申请号：US10835553
申请日：2004-04-29
申请人： Masakatsu Suda , Satoshi Sudou , Toshiyuki Okayasu
发明人： Masakatsu Suda , Satoshi Sudou , Toshiyuki Okayasu
IPC分类号： G01R31/319 , H03K5/13 , H03K5/135 , H03L7/07 , H03L7/081 , H03L7/091 , H04L7/00
CPC分类号： G01R31/31922 , H03K5/133 , H03K5/135 , H03K2005/00026 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H03L7/091 , H04L7/00 , H04L7/0037 , H04L7/0041
摘要： A data sampling apparatus includes plural stages of first variable delay elements for sequentially delaying a data signal by a first delay amount, plural stages of second variable delay elements for sequentially delaying a strobe signal by a second delay amount which is larger than the first delay amount, and a plurality of timing comparators for sampling a plurality of data signals delayed by the plural stages of first variable delay elements by the strobe signal delayed by the second variable delay element of the same stage, wherein the timing comparator includes a dynamic D-FF circuit for latching and outputting the data signal by its parasitic capacitance based on the strobe signal, a buffer for delaying the strobe signal, and a positive feed-back D-FF circuit for latching and outputting the output signal outputted by the dynamic D-FF circuit by its positive feed-back circuit based on the strobe signal delayed.
摘要翻译：数据采样装置包括多级第一可变延迟元件，用于顺序地将数据信号延迟第一延迟量;多级第二可变延迟元件，用于顺序地将选通信号延迟大于第一延迟量的第二延迟量以及多个定时比较器，用于通过由相同级的第二可变延迟元件延迟的选通信号对由多级第一可变延迟元件延迟的多个数据信号进行采样，其中定时比较器包括动态D-FF 用于通过其基于选通信号的寄生电容来锁存和输出数据信号的电路，用于延迟选通信号的缓冲器以及用于锁存和输出由动态D-FF输出的输出信号的正反馈D-FF电路电路由其正反馈电路基于选通信号延迟。

12. 发明授权

US6008686A Power consumption control circuit for CMOS circuit 失效
标题翻译： CMOS电路功耗控制电路
公开(公告)号：US6008686A
公开(公告)日：1999-12-28
申请号：US98223
申请日：1998-06-16
申请人： Masakatsu Suda
发明人： Masakatsu Suda
IPC分类号： G06F1/20 , H01L35/00
CPC分类号： G06F1/206 , Y02B60/1275
摘要： A power consumption control circuit for CMOS circuit for achieving a constant signal propagation delay time in the CMOS circuit by maintaining the same power consumption all the time. A leading edge heater and a trailing edge heater are provided in close proximity to the CMOS circuit. During a time period for a leading edge of an input pulse propagates through the CMOS circuit, the leading edge heater is turned off. During a time period for a trailing edge of the input pulse propagates through the CMOS circuit, the trailing edge heater is turned off. As result, an overall current flowing in the CMOS circuit, leading and trailing edge heaters is unchanged regardless of the repetition rate of the input pulse provided to the CMOS circuit.
摘要翻译：一种用于CMOS电路的功耗控制电路，用于通过始终保持相同的功耗来实现CMOS电路中恒定的信号传播延迟时间。前缘加热器和后缘加热器靠近CMOS电路提供。在输入脉冲的前沿的一段时间内通过CMOS电路传播，前缘加热器被关闭。在输入脉冲的后沿的一段时间内通过CMOS电路传播，后缘加热器被关闭。结果，在CMOS电路中流过的总电流，前缘加热器和后缘加热器都不变，而不管提供给CMOS电路的输入脉冲的重复率如何。

13. 发明授权

US08451034B2 Clock hand-off circuit 有权
标题翻译：时钟切换电路
公开(公告)号：US08451034B2
公开(公告)日：2013-05-28
申请号：US13055203
申请日：2008-07-25
申请人： Tasuku Fujibe , Masakatsu Suda
发明人： Tasuku Fujibe , Masakatsu Suda
IPC分类号： H03L7/00
CPC分类号： H04L7/0338
摘要： A second latch latches the output data of a first latch using a third clock having the same frequency as that of a first clock. A third latch latches the output data of the second latch using a second clock having a frequency N (N represents an integer) times that of the first clock and the third clock. The second clock and the third clock have a frequency division/multiplication relation therebetween.
摘要翻译：第二锁存器使用与第一时钟具有相同频率的第三时钟锁存第一锁存器的输出数据。第三锁存器使用具有与第一时钟和第三时钟的频率N（N表示整数）的频率的第二时钟锁存第二锁存器的输出数据。第二时钟和第三时钟在它们之间具有分频/乘法关系。

14. 发明申请

US20110128052A1 CLOCK HAND-OFF CIRCUIT 有权
标题翻译：时钟手动电路
公开(公告)号：US20110128052A1
公开(公告)日：2011-06-02
申请号：US13055203
申请日：2008-07-25
申请人： Tasuku Fujibe , Masakatsu Suda
发明人： Tasuku Fujibe , Masakatsu Suda
IPC分类号： H03B19/00 , H03L7/00
CPC分类号： H04L7/0338
摘要： A second latch latches the output data of a first latch using a third clock having the same frequency as that of a first clock. A third latch latches the output data of the second latch using a second clock having a frequency N (N represents an integer) times that of the first clock and the third clock. The second clock and the third clock have a frequency division/multiplication relation therebetween.
摘要翻译：第二锁存器使用与第一时钟具有相同频率的第三时钟来锁存第一锁存器的输出数据。第三锁存器使用具有与第一时钟和第三时钟的频率N（N表示整数）的频率的第二时钟锁存第二锁存器的输出数据。第二时钟和第三时钟在它们之间具有分频/乘法关系。

15. 发明授权

US07940072B2 Timing generator and semiconductor test apparatus 失效
标题翻译：定时发生器和半导体测试装置
公开(公告)号：US07940072B2
公开(公告)日：2011-05-10
申请号：US11989713
申请日：2006-07-28
申请人： Masakatsu Suda
发明人： Masakatsu Suda
IPC分类号： G01R31/26
CPC分类号： G01R31/31922 , H03K5/133 , H03K2005/00156 , H03K2005/00195 , H03K2005/00208
摘要： A variable delay circuit has a simple configuration for being incorporated in a timing generator to control a delay time in real time and assure a timing margin. The variable delay circuit of the timing generator includes a delay circuit having a plurality of cascaded clock buffers; a plurality of cascaded data buffers; and data holding circuits for outputting data to the data buffers in accordance with the clock from the delay circuit. The delay amount added to the data by the data buffers is made identical to the delay amount added to the clock by the clock buffers.
摘要翻译：可变延迟电路具有简单的配置，用于并入定时发生器中以实时控制延迟时间并确保定时裕度。定时发生器的可变延迟电路包括具有多个级联时钟缓冲器的延迟电路; 多个级联数据缓冲器; 以及数据保持电路，用于根据来自延迟电路的时钟向数据缓冲器输出数据。由数据缓冲器添加到数据的延迟量与由时钟缓冲器添加到时钟的延迟量相同。

16. 发明授权

US07830191B2 Vernier delay circuit 有权
标题翻译：游标延迟电路
公开(公告)号：US07830191B2
公开(公告)日：2010-11-09
申请号：US12396219
申请日：2009-03-02
申请人： Shoji Kojima , Masakatsu Suda
发明人： Shoji Kojima , Masakatsu Suda
IPC分类号： H03H11/26
CPC分类号： H03K5/131 , H03K2005/00052 , H03K2005/00065 , H03L7/0805 , H03L7/0995
摘要： A ring oscillator oscillates at a frequency determined by an input bias signal. A bias signal adjusting unit produces a bias signal for the ring oscillator using feedback so that the oscillation frequency of the ring oscillator matches a predetermined reference frequency. An individual bias circuit includes a plurality of bias circuits provided for a total of N second variable delay elements, respectively. The bias circuits are configured such that the bias signals can be individually adjusted.
摘要翻译：环形振荡器以由输入偏置信号确定的频率振荡。偏置信号调整单元使用反馈产生环形振荡器的偏置信号，使得环形振荡器的振荡频率与预定的参考频率匹配。单独的偏置电路包括分别为总共N个第二可变延迟元件提供的多个偏置电路。偏置电路被配置成使得可以单独地调整偏置信号。

17. 发明授权

US07800390B2 Load fluctuation correction circuit, electronic device, testing device, and load fluctuation correction method 失效
标题翻译：负载波动校正电路，电子设备，测试装置和负载波动校正方法
公开(公告)号：US07800390B2
公开(公告)日：2010-09-21
申请号：US12370614
申请日：2009-02-13
申请人： Masakatsu Suda
发明人： Masakatsu Suda
IPC分类号： G01R31/02
CPC分类号： H03K19/00346
摘要： Provided is a load fluctuation compensation circuit for compensating a power source voltage supplied to an operation circuit, the load fluctuation compensation circuit including: a periodic signal changing section that receives a power source voltage from a power source shared with the operation circuit, and outputs a changed signal resulting from changing a supplied periodic signal according to the power source voltage; a phase comparator that compares a phase of the periodic signal with a phase of the changed signal outputted from the periodic signal changing section; an initializing section that generates a bias voltage supplied to the periodic signal changing section and adjusts a phase difference between the periodic signal and the changed signal to a preset value, based on the comparison result of the phase comparator; a controller that holds the bias voltage outputted from the initializing section when the phase difference between the periodic signal and the changed signal has become the preset value; a power current consumption circuit that shares a power source with the operation circuit; and a fluctuation compensation section that controls an amount of a power current supplied to the power current consumption circuit, based on the comparison result outputted from the phase comparator while the bias voltage of the initializing section is kept on hold.
摘要翻译：提供一种用于补偿提供给操作电路的电源电压的负载波动补偿电路，所述负载波动补偿电路包括：周期性信号变化部，其从与所述运算电路共用的电源接收电源电压，并输出根据电源电压改变提供的周期信号而产生的改变的信号; 相位比较器，将周期信号的相位与从周期信号变化部输出的变化信号的相位进行比较; 初始化部，其基于所述相位比较器的比较结果，生成提供给所述周期信号变更部的偏置电压，并将所述周期信号与所述变化的信号之间的相位差调整为预设值; 控制器，当周期信号和改变信号之间的相位差成为预设值时，保持从初始化部分输出的偏置电压; 与所述运行电路共用电源的电力消耗电路; 以及波动补偿部，其基于从所述初始化部的所述偏置电压保持在所述相位比较器输出的比较结果来控制供给所述电力消耗电路的电力量的量。

18. 发明授权

US07665004B2 Timing generator and semiconductor testing apparatus 有权
标题翻译：定时发生器和半导体测试仪器
公开(公告)号：US07665004B2
公开(公告)日：2010-02-16
申请号：US11570042
申请日：2005-06-06
申请人： Masakatsu Suda , Masahiro Ishida , Daisuke Watanabe
发明人： Masakatsu Suda , Masahiro Ishida , Daisuke Watanabe
IPC分类号： G06F11/00
CPC分类号： G01R31/31709 , G01R31/31922
摘要： A timing generator that needs no analog circuit for adding jitters and allows the circuit scale and power consumption to be reduced. There are included a counter for performing a counting operation synchronized with a reference clock signal: a timing memory for outputting respective data corresponding to the quotient and remainder resulting from dividing the time from the front of a basic period until a generation of a timing edge by the period of the reference clock signal: a coincidence detecting circuit for outputting a signal that exhibits a high level when the count value of the counter coincides with the quotient: a jitter generating circuit for outputting as a jitter amplitude value: adders for adding a time corresponding to the remainder and a time represented by the jitter amplitude value outputted from the jitter generating circuit: and a variable delay circuit for delaying the output signal from the coincidence detecting circuit by the time represented by the addition result of the adders and outputting the delayed output signal.
摘要翻译：定时发生器不需要模拟电路来加入抖动，并且可以减小电路规模和功耗。包括用于执行与参考时钟信号同步的计数操作的计数器：定时存储器，用于输出与商相对应的各个数据，以及由从基本周期的前方划分到时间边缘的产生之前的时间，参考时钟信号的周期：当计数器的计数值与商相符时，输出呈现高电平的信号的一致检测电路：用于输出抖动振幅值的抖动发生电路：用于添加时间的加法器对应于剩余时间和由抖动发生电路输出的抖动振幅值表示的时间;以及可变延迟电路，用于将来自符合检测电路的输出信号延迟由加法器的相加结果表示的时间，并输出延迟输出信号。

19. 发明申请

US20100019795A1 VARIABLE DELAY CIRCUIT, TIMING GENERATOR AND SEMICONDUCTOR TESTING APPARATUS 有权
标题翻译：可变延迟电路，时序发生器和半导体测试装置
公开(公告)号：US20100019795A1
公开(公告)日：2010-01-28
申请号：US12310335
申请日：2007-08-15
申请人： Masakatsu Suda
发明人： Masakatsu Suda
IPC分类号： G01R31/26 , H03H11/26 , H03L7/00
CPC分类号： G01R31/3016 , G01R31/31922 , G01R31/31937 , H03K5/133 , H03K2005/00032
摘要： The accuracy of the delay amount to be imparted to a timing signal is improved by increasing the delay amount obtained by a first stage of a delay element.A variable delay 50 which comprises a DA converter 51 which supplies current 51 based on delay setting data; a delay element 53 which imparts a delay amount Tpd to a prescribed signal and outputs the signal; and a bias circuit 52 which is connected such that the amount of current flown in the DA converter 51 and the amount of current flown in the delay element 53 become equal, wherein the DA converter 51 allows the relationship between the delay setting data DATA and the current Id to be hyperbolic (inversely proportional). As a result, the relationship between the delay setting data DATA and the delay amount Tpd can be linear, whereby the delay amount obtained by a first stage of the delay element can be widened.
摘要翻译：通过增加由延迟元件的第一级获得的延迟量来提高赋予定时信号的延迟量的精度。可变延迟器50，其包括：基于延迟设定数据提供电流51的DA转换器51; 延迟元件53，其将延迟量Tpd赋予规定的信号，并输出该信号; 以及偏置电路52，其连接成使得在DA转换器51中流动的电流量和在延迟元件53中流动的电流量相等，其中DA转换器51允许延迟设置数据DATA和电流Id为双曲线（反比例）。结果，延迟设定数据DATA与延迟量Tpd之间的关系可以是线性的，由此延迟元件的第一级获得的延迟量可以被加宽。

20. 发明授权

US07492198B2 Phase-locked loop circuit, delay locked loop circuit, timing generator, semiconductor test instrument, and semiconductor integrated circuit 失效
标题翻译：锁相环电路，延迟锁定环路电路，定时发生器，半导体测试仪器和半导体集成电路
公开(公告)号：US07492198B2
公开(公告)日：2009-02-17
申请号：US10493130
申请日：2002-10-18
申请人： Masakatsu Suda
发明人： Masakatsu Suda
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/089 , H03L7/093 , H03L7/0995
摘要： A PLL and DLL are designed such that the power consumption is reduced, the size is reduced, the band width of the locked loop is increased, and the reliability is improved. There are provided a phase comparator for measuring the value of a feedback signal in synchronism with an input signal and outputting a phase signal representing the lead or lag of the phase of the feedback signal, a counter for increasing by one the number of bits representing “H” in a control signal when the phase signal represents the lead of the phase or decreasing by one the number of bits representing “H” in the control signal when the phase signal represents the lag of the phase, and a ring oscillator for increasing the oscillation period when the number of bits representing “H” in the control signal increases or decreasing the oscillation period when the number of bits representing “H” decreases.
摘要翻译： PLL和DLL被设计为使得功耗降低，尺寸减小，锁定环的带宽增加，并且可靠性得到改善。提供了一个相位比较器，用于与输入信号同步地测量反馈信号的值，并输出表示反馈信号的相位的超前或滞后的相位信号，计数器增加一个表示“ 当相位信号表示相位的引导，或者当相位信号表示相位的滞后时，在控制信号中表示“H”的比特数减少1时，控制信号中存在“H”;以及环形振荡器，当表示“H”的比特数减少时，在控制信号中表示“H”的比特数增加或减小振荡周期时的振荡周期。

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