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11. 发明申请

US20060273460A1 Method and structure for determining thermal cycle reliability 有权
标题翻译：确定热循环可靠性的方法和结构
公开(公告)号：US20060273460A1
公开(公告)日：2006-12-07
申请号：US11502196
申请日：2006-08-10
申请人： Ronald Filippi , Jason Gill , Vincent McGahay , Paul McLaughlin , Conal Murray , Hazara Rathore , Thomas Shaw , Ping-Chuan Wang
发明人： Ronald Filippi , Jason Gill , Vincent McGahay , Paul McLaughlin , Conal Murray , Hazara Rathore , Thomas Shaw , Ping-Chuan Wang
IPC分类号： H01L23/58 , H01L23/48 , H01L29/10 , H01L23/52 , H01L29/40
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
摘要翻译：用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。测试结构热循环，测量结构的产量。基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

12. 发明申请

US20050227380A1 Control of liner thickness for improving thermal cycle reliability 失效
标题翻译：控制衬套厚度，提高热循环的可靠性
公开(公告)号：US20050227380A1
公开(公告)日：2005-10-13
申请号：US10815418
申请日：2004-04-01
申请人： Ronald Filippi , Lynne Gignac , Vincent McGahay , Conal Murray , Hazara Rathore , Thomas Shaw , Ping-Chuan Wang
发明人： Ronald Filippi , Lynne Gignac , Vincent McGahay , Conal Murray , Hazara Rathore , Thomas Shaw , Ping-Chuan Wang
IPC分类号： G06F13/28
CPC分类号： G01R31/2881
摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.
摘要翻译：公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。在结构中感兴趣的位置确定菌株。在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。可以根据结果进行预测和设计更改。

13. 发明申请

US20060027842A1 Control of liner thickness for improving thermal cycle reliability 有权
公开(公告)号：US20060027842A1
公开(公告)日：2006-02-09
申请号：US11248719
申请日：2005-10-12
申请人： Ronald Filippi , Lynne Gignac , Vincent McGahay , Conal Murray , Hazara Rathore , Thomas Shaw , Ping-Chuan Wang
发明人： Ronald Filippi , Lynne Gignac , Vincent McGahay , Conal Murray , Hazara Rathore , Thomas Shaw , Ping-Chuan Wang
IPC分类号： H01L29/76
CPC分类号： G01R31/2881
摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

14. 发明申请

US20130176073A1 BACK-END ELECTRICALLY PROGRAMMABLE FUSE 有权
标题翻译：后端电可编程保险丝
公开(公告)号：US20130176073A1
公开(公告)日：2013-07-11
申请号：US13348011
申请日：2012-01-11
申请人： Junjing Bao , Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald Filippi , Stephan Grunow , Naftali E. Lustig , Dan Moy , Andrew H. Simon
发明人： Junjing Bao , Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald Filippi , Stephan Grunow , Naftali E. Lustig , Dan Moy , Andrew H. Simon
IPC分类号： H01H37/76 , H01L21/768 , B44C1/22 , H01L23/525
CPC分类号： H01L23/5256 , H01H2085/0275 , H01L21/76805 , H01L21/76807 , H01L21/76811 , H01L21/76816 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.
摘要翻译：公开了一种BEOL电子熔断器，其可靠地吹入通孔并且甚至可以在最窄的节距BEOL层中形成。 BEOL电子熔断器可以利用线路第一双镶嵌工艺形成，以创建一个亚光刻通孔，作为电子熔丝的可编程链路。亚光刻通孔可以使用标准光刻图案化，并且通孔的横截面可以被调谐以匹配目标编程电流。

15. 发明申请

US20070115018A1 STRUCTURE AND METHOD FOR MONITORING STRESS-INDUCED DEGRADATION OF CONDUCTIVE INTERCONNECTS 有权
标题翻译：用于监测导电互连的应力诱导降解的结构和方法
公开(公告)号：US20070115018A1
公开(公告)日：2007-05-24
申请号：US11163948
申请日：2005-11-04
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

16. 发明授权

US09685404B2 Back-end electrically programmable fuse 有权
公开(公告)号：US09685404B2
公开(公告)日：2017-06-20
申请号：US13348011
申请日：2012-01-11
申请人： Junjing Bao , Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald Filippi , Stephan Grunow , Naftali E. Lustig , Dan Moy , Andrew H. Simon
发明人： Junjing Bao , Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald Filippi , Stephan Grunow , Naftali E. Lustig , Dan Moy , Andrew H. Simon
IPC分类号： H01L21/768 , H01L23/525 , H01L23/522 , H01H85/02
CPC分类号： H01L23/5256 , H01H2085/0275 , H01L21/76805 , H01L21/76807 , H01L21/76811 , H01L21/76816 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

17. 发明授权

US08056039B2 Interconnect structure for integrated circuits having improved electromigration characteristics 有权
标题翻译：具有改进的电迁移特性的集成电路的互连结构
公开(公告)号：US08056039B2
公开(公告)日：2011-11-08
申请号：US12128973
申请日：2008-05-29
申请人： Kaushik Chanda , Ronald Filippi , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
发明人： Kaushik Chanda , Ronald Filippi , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
IPC分类号： G06F17/50
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w1, and one or more segments formed at one or more additional widths, w2 . . . wN, with the first width being narrower than each of the one or more additional widths; wherein the relationship of the total length, L1, of the one or more conductive segments formed at the first width to the total lengths, L2 . . . LN, of the one or more conductive segments formed at the one or more additional widths is selected such that, for a given magnitude of current carried by the conductive line, a critical length with respect to an electromigration short-length effect benefit is maintained such that a total length of the conductive line, L=L1+L2+ . . . +LN, meets a minimum desired design length regardless of the critical length.
摘要翻译：用于集成电路（IC）装置的互连结构包括细长的导电线，其包括形成在第一宽度w 1处的一个或多个段以及以一个或多个附加宽度w2形成的一个或多个段。。。 wN，其中第一宽度比一个或多个附加宽度中的每一个窄; 其中形成在第一宽度处的一个或多个导电段的总长度L1与总长度L2的关系。。。选择以一个或多个附加宽度形成的一个或多个导电段的LN，使得对于给定的导电线承载的电流，相对于电迁移短长度效应益处的临界长度被保持为导线的总长度L = L1 + L2 +。。。 + LN，无论临界长度如何，满足最小设计长度。

18. 发明申请

US20080107149A1 Method for monitoring stress-induced degradation of conductive interconnects 失效
标题翻译：用于监测导电互连的应力诱导退化的方法
公开(公告)号：US20080107149A1
公开(公告)日：2008-05-08
申请号：US12004011
申请日：2007-12-19
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
IPC分类号： G01N25/72 , G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

19. 发明申请

US20120100712A1 STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME 失效
标题翻译：半导体器件的电源结构及其制造方法
公开(公告)号：US20120100712A1
公开(公告)日：2012-04-26
申请号：US13342221
申请日：2012-01-03
申请人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
发明人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
IPC分类号： H01L21/76
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76847 , H01L21/76852 , H01L23/5286 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.
摘要翻译：本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。还提供了制造半导体结构的方法。

20. 发明授权

US06803662B2 Low dielectric constant material reinforcement for improved electromigration reliability 失效
标题翻译：低介电常数材料增强，提高电迁移可靠性
公开(公告)号：US06803662B2
公开(公告)日：2004-10-12
申请号：US10026117
申请日：2001-12-21
申请人： Ping-Chuan Wang , Kevin H. Brelsford , Ronald Filippi
发明人： Ping-Chuan Wang , Kevin H. Brelsford , Ronald Filippi
IPC分类号： H01L2348
CPC分类号： H01L23/522 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A reinforced semiconductor interconnect structure, having the following components: (1) A first metal interconnect disposed in a first material, the first metal interconnect having a line portion and at least one via portion, an anode section and a cathode section, the via portion of the first metal interconnect located in the anode section, the line portion of the first metal interconnect having a top, bottom and terminus side, wherein at least a part of the bottom side of the line portion of the first metal interconnect in contact with the first dielectric; and (2) a first reinforcement disposed in the first material, the first reinforcement in contact with at least the bottom side of the first metal interconnect, the first reinforcement comprising a second material, the second material being electrically nonconductive; and wherein the second material has a greater mechanical rigidity than the first material.
摘要翻译：一种增强的半导体互连结构，具有以下部件：（1）设置在第一材料中的第一金属互连件，所述第一金属互连件具有线部分和至少一个通孔部分，阳极部分和阴极部分，所述通孔部分位于阳极部分中的第一金属互连件，第一金属互连线的线部分具有顶部，底部和末端侧，其中第一金属互连线路部分的底侧的至少一部分与第一电介质; 和（2）设置在所述第一材料中的第一加强件，所述第一加强件至少与所述第一金属互连件的底侧相接触，所述第一加强件包括第二材料，所述第二材料是不导电的; 并且其中所述第二材料具有比所述第一材料更大的机械刚度。

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