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11. 发明授权

US5554876A Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing method thereof 失效
标题翻译：包含氧化硅膜和氮化氧化膜作为栅极绝缘膜的场效应晶体管及其制造方法
公开(公告)号：US5554876A
公开(公告)日：1996-09-10
申请号：US292591
申请日：1994-08-16
申请人： Shigeru Kusunoki , Masahide Inuishi
发明人： Shigeru Kusunoki , Masahide Inuishi
IPC分类号： H01L21/266 , H01L21/28 , H01L21/314 , H01L21/336 , H01L29/51 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28185 , H01L21/266 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L29/512 , H01L29/518 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7836 , H01L29/78621 , Y10S257/90
摘要： An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.
摘要翻译：一种N型场效应晶体管，其具有对热载流子的较高的电阻率，并且即使在低栅极电压下使用时也具有更高的电流处理能力，并且提供了制造这种晶体管的方法。在排水雪崩热载体注入区域上形成氮化氧化物膜。与氧化硅膜相比，氮化氧化物膜对排水雪崩热载流子具有高度阻力。氧化硅膜形成在通道热电子注入区域上。与氮化氧化物膜相比，氧化硅膜对沟道热电子具有高度的阻力。栅绝缘膜的主要部分是氧化硅膜。与氮化氧化物膜相比，氧化硅膜在低栅极电压下表现出更高的电流处理能力。

12. 发明授权

US5536665A Method of manufacturing a semiconductor device with double structured well 失效
标题翻译：制造具有双重结构井的半导体器件的方法
公开(公告)号：US5536665A
公开(公告)日：1996-07-16
申请号：US442928
申请日：1995-05-17
申请人： Shigeki Komori , Takashi Kuroi , Masahide Inuishi
发明人： Shigeki Komori , Takashi Kuroi , Masahide Inuishi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L21/266
CPC分类号： H01L27/0921 , H01L27/10805 , Y10S148/085
摘要： A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.
摘要翻译：半导体器件包括p型硅衬底，形成在硅衬底的主表面中的p型第一阱和在硅衬底的主表面中靠近第一阱形成的n型第二阱。在第二阱内形成第三阱p型，此外，形成包含比第一阱高的浓度的p型杂质的导电层，直接在第一阱和第二阱的正下方延伸。根据该结构，即使注入少量载流子，它们在导电层中复合并消失，从而防止载流子注入到第一阱中。结果，防止了由于少数载流子的注入引起的各种不利现象，并且提供了具有稳定的器件特性和高集成度的半导体器件。

13. 发明授权

US5200353A Method of manufacturing a semiconductor device having trench capacitor 失效
标题翻译：制造具有沟槽电容器的半导体器件的方法
公开(公告)号：US5200353A
公开(公告)日：1993-04-06
申请号：US754296
申请日：1991-09-04
申请人： Masahide Inuishi
发明人： Masahide Inuishi
IPC分类号： H01L27/108
CPC分类号： H01L27/10829
摘要： A semiconductor memory device comprises a semiconductor substrate having a trench, first polysilicon serving as a charge storage region formed through an insulating film in an inner portion of the trench, and second polysilicon serving as a capacitor electrode formed through an insulating film inside of the first polysilicon. An impurity contact region connects the charge storage region to a transfer gate transistor in the surface adjacent the trench so that information charges are transferred. A method for manufacturing such a semiconductor memory device includes forming a trench in the major surface of the semiconductor substrate and forming a first insulating layer in an inner portion of the trench. On at least one sidewall of the trench, the first insulating layer begins at a distance below the upper end of the trench. The impurity contact region is formed by obliquely implanting ions in the region of the sidewall above the first insulating layer and in a portion of the major surface of the substrate. The first polysilicon layer, which serves as the charge storage region of the capacitor, is formed in the trench in contact with the impurity contact region. The insulating film and the second polysilicon electrode of the capacitor are then formed on the first polysilicon layer.
摘要翻译：半导体存储器件包括具有沟槽的半导体衬底，用作在沟槽内部通过绝缘膜形成的电荷存储区域的第一多晶硅，以及用作电容器电极的第二多晶硅，其通过第一多晶硅杂质接触区域将电荷存储区域连接到与沟槽相邻的表面中的传输栅极晶体管，从而传送信息电荷。一种用于制造这种半导体存储器件的方法包括在半导体衬底的主表面上形成沟槽，并在沟槽的内部形成第一绝缘层。在沟槽的至少一个侧壁上，第一绝缘层在沟槽的上端下方的距离处开始。杂质接触区域通过在第一绝缘层上方的侧壁的区域中以及衬底的主表面的一部分中倾斜地注入离子而形成。作为电容器的电荷存储区域的第一多晶硅层形成在与杂质接触区域接触的沟槽中。然后在第一多晶硅层上形成电容器的绝缘膜和第二多晶硅电极。

14. 发明授权

US5852327A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5852327A
公开(公告)日：1998-12-22
申请号：US709592
申请日：1996-09-09
申请人： Shigeki Komori , Tomohiko Yamashita , Masahide Inuishi
发明人： Shigeki Komori , Tomohiko Yamashita , Masahide Inuishi
IPC分类号： H01L21/768 , H01L23/48 , H01L29/78
CPC分类号： H01L21/74
摘要： In a semiconductor substrate of a semiconductor device, a plural impurity layers of the same conductivity type as the substrate are formed. An impurity region of an opposite conductivity type penetrates at least one of the impurity layers to a certain depth from the main surface of the semiconductor substrate. The bottom surface of the impurity region terminates between the impurity layers where the impurity concentration is lower. A contact conductor is led out from the impurity region.
摘要翻译：在半导体器件的半导体衬底中，形成与衬底相同导电类型的多个杂质层。相反导电类型的杂质区域从半导体衬底的主表面穿透至少一个杂质层至一定的深度。杂质区域的底表面在杂质浓度较低的杂质层之间终止。接触导体从杂质区域引出。

15. 发明授权

US5200918A Static semiconductor memory with polysilicon source drain transistors 失效
标题翻译：具有多晶硅源极漏极晶体管的静态半导体存储器
公开(公告)号：US5200918A
公开(公告)日：1993-04-06
申请号：US873148
申请日：1992-04-24
申请人： Tomohisa Wada , Masahide Inuishi
发明人： Tomohisa Wada , Masahide Inuishi
IPC分类号： H01L27/11 , H01L29/45
CPC分类号： H01L27/1112 , H01L29/456
摘要： A static type semiconductor memory device includes memory cells each including a pair of field effect transistors (FETs) each having a gate electrode cross-coupled to a drain region connected to a power source terminal by way of a load register. The memory device includes a semiconductor substrate of a first conductivity type, polycrystal silicon layers containing impurities of a second conductivity type and first and second FETs. The polycrystal silicon layers are formed with a spacing from one another for defining a channel region on the substrate. The first and second FETs are formed on the substrate and each includes source and drain regions of a second conductivity type and a gate electrode. The source and drain regions are formed below the polycrystal silicon layers by introducing impurities from the polycrystal silicon layers into the substrate. The gate electrode is formed on the channel region and the polycrystal silicon layers with a gate insulating film interposed. The drain region of the first FET and the gate electrode of the second FET are cross-coupled to each other through the polycrystal silicon layer, while the drain region of the second FET and the gate electrode of the first FET are also similarly cross-coupled to each other. The parasitic resistance of the source and drain regions can be reduced, while the leakage current due to the short channel effect can also be reduced. Since the memory cell is freed of asymmetries, a static type semiconductor memory device is provided with is improved both in stability and data storage property.
摘要翻译：静态型半导体存储器件包括各自包括一对场效应晶体管（FET）的存储单元，每个场效应晶体管（FET）具有与通过负载寄存器连接到电源端子的漏极区域交叉耦合的栅电极。存储器件包括第一导电类型的半导体衬底，含有第二导电类型杂质的多晶硅层和第一和第二FET。多晶硅层形成为彼此间隔开以限定衬底上的沟道区。第一和第二FET形成在衬底上，并且每个包括第二导电类型的栅极和漏极区域和栅电极。通过将多晶硅层中的杂质引入衬底中，在多晶硅层的下面形成源区和漏区。栅极电极形成在沟道区域和多晶硅层之间，并具有栅绝缘膜。第一FET的漏极区域和第二FET的栅极电极通过多晶硅层彼此交叉耦合，而第二FET的漏极区域和第一FET的栅极电极也类似地交叉耦合对彼此。可以减小源极和漏极区域的寄生电阻，同时也可以减小由于短沟道效应导致的漏电流。由于存储单元没有不对称性，因此提供了稳定性和数据存储性能的静态型半导体存储器件。

16. 发明授权

US5166763A Static type semiconductor memory device and method of manufacturing thereof 失效
标题翻译：静电型半导体存储器件及其制造方法
公开(公告)号：US5166763A
公开(公告)日：1992-11-24
申请号：US693023
申请日：1991-04-30
申请人： Tomohisa Wada , Masahide Inuishi
发明人： Tomohisa Wada , Masahide Inuishi
IPC分类号： H01L27/11 , H01L29/45
CPC分类号： H01L29/456 , H01L27/1112 , Y10S257/903
摘要： A static type semiconductor memory device includes memory cells each including a pair of field effect transistors (FETs) each having a gate electrode cross-coupled to a drain region connected to a power source terminal by way of a load register. The memory device includes a semiconductor substrate of a first conductivity type, polycrystal silicon layers containing impurities of a second conductivity type and first and second FETs. The polycrystal silicon layers are formed with a spacing from one another for defining a channel region on the substrate. The first and second FETs are formed on the substrate and each includes source and drain regions of a second conductivity type and a gate electrode. The source and drain regions are formed below the polycrystal silicon layers by introducing impurities from the polycrystal silicon layers into the substrate. The gate electrode is formed on the channel region and the polycrystal silicon layers with a gate insulating film interposed. The drain region of the first FET and the gate electrode of the second FET are cross-coupled to each other through the polycrystal silicon layer, while the drain region of the second FET and the gate electrode of the first FET are also similarly cross-coupled to each other. The parasitic resistance of the source and drain regions can be reduced, while the leakage current due to the short channel effect can also be reduced. Since the memory cell is freed of asymmetries, a static type semiconductor memory device is provided with is improved both in stability and data storage property.
摘要翻译：静态型半导体存储器件包括各自包括一对场效应晶体管（FET）的存储单元，每个场效应晶体管（FET）具有与通过负载寄存器连接到电源端子的漏极区域交叉耦合的栅电极。存储器件包括第一导电类型的半导体衬底，含有第二导电类型杂质的多晶硅层和第一和第二FET。多晶硅层形成为彼此间隔开以限定衬底上的沟道区。第一和第二FET形成在衬底上，并且每个包括第二导电类型的栅极和漏极区域和栅电极。通过将多晶硅层中的杂质引入衬底中，在多晶硅层的下面形成源区和漏区。栅极电极形成在沟道区域和多晶硅层之间，并具有栅绝缘膜。第一FET的漏极区域和第二FET的栅极电极通过多晶硅层彼此交叉耦合，而第二FET的漏极区域和第一FET的栅极电极也类似地交叉耦合对彼此。可以减小源极和漏极区域的寄生电阻，同时也可以减小由于短沟道效应导致的漏电流。由于存储单元没有不对称性，因此提供了稳定性和数据存储性能的静态型半导体存储器件。

17. 发明授权

US5648284A Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing method thereof 失效
标题翻译：包含氧化硅膜和氮化氧化膜作为栅极绝缘膜的场效应晶体管及其制造方法
公开(公告)号：US5648284A
公开(公告)日：1997-07-15
申请号：US653090
申请日：1996-05-24
申请人： Shigeru Kusunoki , Masahide Inuishi
发明人： Shigeru Kusunoki , Masahide Inuishi
IPC分类号： H01L21/266 , H01L21/28 , H01L21/314 , H01L21/336 , H01L29/51 , H01L29/78 , H01L29/786 , H01L21/265
CPC分类号： H01L21/28185 , H01L21/266 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L29/512 , H01L29/518 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7836 , H01L29/78621 , Y10S257/90
摘要： An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.
摘要翻译：一种N型场效应晶体管，其具有对热载流子的较高的电阻率，并且即使在低栅极电压下使用时也具有更高的电流处理能力，并且提供了制造这种晶体管的方法。在排水雪崩热载体注入区域上形成氮化氧化物膜。与氧化硅膜相比，氮化氧化物膜对排水雪崩热载流子具有高度阻力。氧化硅膜形成在通道热电子注入区域上。与氮化氧化物膜相比，氧化硅膜对沟道热电子具有高度的阻力。栅绝缘膜的主要部分是氧化硅膜。与氮化氧化物膜相比，氧化硅膜在低栅极电压下表现出更高的电流处理能力。

18. 发明授权

US5446305A Semiconductor device with double structured well 失效
标题翻译：具有双重结构井的半导体器件
公开(公告)号：US5446305A
公开(公告)日：1995-08-29
申请号：US240282
申请日：1994-05-09
申请人： Shigeki Komori , Takashi Kuroi , Masahide Inuishi
发明人： Shigeki Komori , Takashi Kuroi , Masahide Inuishi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L27/02 , H01L29/70
CPC分类号： H01L27/0921 , H01L27/10805 , Y10S148/085
摘要： A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.
摘要翻译：半导体器件包括p型硅衬底，形成在硅衬底的主表面中的p型第一阱和在硅衬底的主表面中靠近第一阱形成的n型第二阱。在第二阱内形成第三阱p型，此外，形成包含比第一阱高的浓度的p型杂质的导电层，直接在第一阱和第二阱的正下方延伸。根据该结构，即使注入少量载流子，它们在导电层中复合并消失，从而防止载流子注入到第一阱中。结果，防止了由于少数载流子的注入引起的各种不利现象，并且提供了具有稳定的器件特性和高集成度的半导体器件。

19. 发明授权

US5217913A Method of manufacturing an MIS device having lightly doped drain structure and conductive sidewall spacers 失效
标题翻译：制造具有轻掺杂漏极结构和导电侧壁间隔物的MIS器件的方法
公开(公告)号：US5217913A
公开(公告)日：1993-06-08
申请号：US896535
申请日：1992-06-09
申请人： Kiyoto Watabe , Katsuyoshi Mitsui , Masahide Inuishi
发明人： Kiyoto Watabe , Katsuyoshi Mitsui , Masahide Inuishi
IPC分类号： H01L29/417 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/41775 , H01L29/7836
摘要： A MOS FET comprises a pair of source and drain impurity regions, a gate oxide film and a gate electrode. The source and drain regions have an LDD structure in which high concentration impurity regions and low concentration impurity regions are set off. The gate electrode is formed to extend over the channel region and contains sidewalls overlying the low concentration impurity regions. In addition, portions of the gate oxide film located between the sidewalls of the gate electrode and the respective low concentration impurity regions are formed to have a film thickness larger than that of the portion located between the gate electrode and the channel region. The thick portion of the oxide film underlying the gate sidewalls form a charge storage layer which reduces the resistance of the low impurity concentration region while minimizing the gate capacitance. In another example, conductive sidewall spacers are formed on sidewalls of a gate electrode through an insulating film. The sidewall spacers are connected with source and drain electrode connections or directly with source and drain impurity regions. Hot carriers generated near the drain are taken out from a gate insulating layer through conductive sidewall spacers. Accordingly, increase of the resistance due to trapped hot carriers can be prevented.
摘要翻译： MOS FET包括一对源极和漏极杂质区域，栅氧化物膜和栅极电极。源区和漏区具有LDD结构，其中高浓度杂质区和低浓度杂质区被引出。栅电极形成为在沟道区域上延伸并且包含覆盖低浓度杂质区的侧壁。此外，位于栅电极的侧壁和各低浓度杂质区之间的栅极氧化膜的部分形成为具有大于位于栅电极和沟道区之间的部分的膜厚。栅极侧壁下方的氧化膜的厚部形成电荷存储层，从而降低了低杂质浓度区域的电阻同时最小化栅极电容。在另一示例中，通过绝缘膜在导电侧壁间隔物形成在栅电极的侧壁上。侧壁间隔件与源极和漏极连接或直接与源极和漏极杂质区连接。在漏极附近产生的热载流子通过导电侧壁间隔物从栅绝缘层中取出。因此，可以防止由于被捕获的热载体引起的电阻的增加。

20. 发明授权

US5146291A MIS device having lightly doped drain structure 失效
标题翻译： MIS器件具有轻掺杂漏极结构
公开(公告)号：US5146291A
公开(公告)日：1992-09-08
申请号：US399947
申请日：1989-08-31
申请人： Kiyoto Watabe , Katsuyoshi Mitsui , Masahide Inuishi
发明人： Kiyoto Watabe , Katsuyoshi Mitsui , Masahide Inuishi
IPC分类号： H01L29/417 , H01L29/78
CPC分类号： H01L29/41775 , H01L29/7835 , H01L29/7836 , Y10S257/90
摘要： A MOS FET comprises a pair of source and drain impurity regions, a gate oxide film and a gate electrode. The source and drain regions have an LDD structure in which high concentration impurity regions and low concentration impurity regions are set off. The gate electrode is formed to extend over the channel region and contains sidewalls overlying the low concentration impurity regions. In addition, portions of the gate oxide film located between the sidewalls of the gate electrode and the respective low concentration impurity regions are formed to have a film thickness larger than that of the portion located between the gate electrode and the channel region. The thick portion of the oxide film underlying the gate sidewalls form a charge storage layer which reduces the resistance of the low impurity concentration region while minimizing the gate capacitance. In another example, conductive sidewall spacers are formed on sidewalls of a gate electrode through an insulating film. The sidewall spacers are connected with source and drain electrode connections or directly with source and drain impurity regions. Hot carriers generated near the drain are taken out from a gate insulating layer through conductive sidewall spacers. Accordingly, increase of the resistance due to trapped hot carriers can be prevented.
摘要翻译： MOS FET包括一对源极和漏极杂质区域，栅氧化物膜和栅极电极。源区和漏区具有LDD结构，其中高浓度杂质区和低浓度杂质区被引出。栅电极形成为在沟道区域上延伸并且包含覆盖低浓度杂质区的侧壁。此外，位于栅电极的侧壁和各低浓度杂质区之间的栅极氧化膜的部分形成为具有大于位于栅电极和沟道区之间的部分的膜厚。栅极侧壁下方的氧化膜的厚部形成电荷存储层，从而降低了低杂质浓度区域的电阻同时最小化栅极电容。在另一示例中，通过绝缘膜在导电侧壁间隔物形成在栅电极的侧壁上。侧壁间隔件与源极和漏极连接或直接与源极和漏极杂质区连接。在漏极附近产生的热载流子通过导电侧壁间隔物从栅绝缘层中取出。因此，可以防止由于被捕获的热载体引起的电阻的增加。

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