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11. 发明授权

US5260225A Integrated infrared sensitive bolometers 失效
标题翻译：集成红外敏感测辐射热计
公开(公告)号：US5260225A
公开(公告)日：1993-11-09
申请号：US973606
申请日：1992-11-09
申请人： Michael S. Liu , Jeffrey S. Haviland , Cheisan J. Yue
发明人： Michael S. Liu , Jeffrey S. Haviland , Cheisan J. Yue
IPC分类号： G01J1/02 , G01J5/02 , G01J5/20 , H01C7/02 , H01L31/0248 , H01L31/0368 , H01L31/18 , H01L37/02 , H01L3/18
CPC分类号： G01J5/20 , H01L31/03682 , H01L31/1804 , Y02E10/546 , Y02E10/547 , Y02P70/521
摘要： A method for fabricating an integrated infrared sensitive bolometer having a polycrystalline element whereby an oxide region deposited on silicon nitride covered with a first polysilicon layer which is etched to provide a location for a bolometer element. A second polysilicon layer is deposited and doped to achieve a desired temperature coefficient of resistivity of 1 to 2%/.degree.C. The second polysilicon layer forms an IR sensitive element over the oxide region. Openings are etched in the IR sensitive element to permit an etchant to remove the oxide region resulting in the sensitive element being suspended over a cavity.
摘要翻译：一种用于制造具有多晶元件的集成红外敏感测辐射热计的方法，由此沉积在氮化硅上的氧化物区域被第一多晶硅层覆盖，该第一多晶硅层被蚀刻以提供测辐射热计元件的位置。沉积和掺杂第二多晶硅层以实现所需的电阻率温度系数为1至2％/℃。第二多晶硅层在氧化物区域上形成IR敏感元件。在IR敏感元件中蚀刻开口以允许蚀刻剂去除氧化物区域，导致敏感元件悬浮在空腔上。

12. 发明授权

US5519336A Method for electrically characterizing the insulator in SOI devices 失效
标题翻译：用于在SOI器件中表征绝缘体的方法
公开(公告)号：US5519336A
公开(公告)日：1996-05-21
申请号：US356041
申请日：1994-12-06
申请人： Michael S. Liu , Cheisan J. Yue , Paul S. Fechner
发明人： Michael S. Liu , Cheisan J. Yue , Paul S. Fechner
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66 , G01R19/08
CPC分类号： G01R31/2831 , G01R31/2648 , H01L22/14
摘要： A rapid method for determining electrical characteristics of SOI wafers whereby the silicon substrate acts as a gate and tungsten probes make a source and drain connection at the top silicon surface to form a point contact transistor. Drain current is measured as a function of gate voltage as gate voltage is swept from negative to positive values. The subthreshold voltage current characteristic exhibits a minimum drain current occurring close to zero gate voltage. The tungsten probe point contacts apparently are responding to both electron and hole conduction or simply intrinsic CMOS behavior. Using current voltage characteristics, estimates may be made of interface state density and oxide charge density. Analysis of the gate voltage shift for minimum drain current allows determination of threshold voltage shift due to radiation.
摘要翻译：用于确定SOI晶片的电特性的快速方法，其中硅衬底用作栅极和钨探针，在顶部硅表面处形成源极和漏极连接，以形成点接触晶体管。当栅极电压从负值扫描到正值时，将漏极电流作为栅极电压的函数进行测量。亚阈值电压电流特性表现出接近零栅极电压的最小漏极电流。钨探针点接触显然是响应于电子和空穴传导或简单的本征CMOS行为。使用电流电压特性，可以估计接口态密度和氧化物电荷密度。分析最小漏极电流的栅极电压偏移允许确定由于辐射导致的阈值电压偏移。

13. 发明授权

US5234861A Method for forming variable width isolation structures 失效
标题翻译：形成可变宽度隔离结构的方法
公开(公告)号：US5234861A
公开(公告)日：1993-08-10
申请号：US668013
申请日：1991-03-12
申请人： Roger L. Roisen , Curtis H. Rahn , John B. Straight , Michael S. Liu
发明人： Roger L. Roisen , Curtis H. Rahn , John B. Straight , Michael S. Liu
IPC分类号： H01L21/763
CPC分类号： H01L21/763 , Y10S438/902
摘要： An isolation structure as well as a method for using and fabricating an isolation structure in an active layer deposited on a substrate the method of fabrication including the steps of forming a buried oxide layer in the active layer adjacent the substrate, forming an isolation trench in the active layer by etching at least up to and optionally into the substrate, forming a dielectric isolation layer on the exposed surfaces of the trench, removing the dielectric isolation layer from the bottom of the trench, and forming an isolation structure by epitaxially growing monocrystalline silicon in the trench.
摘要翻译：隔离结构以及在沉积在衬底上的有源层中使用和制造隔离结构的方法，其制造方法包括以下步骤：在邻近衬底的有源层中形成掩埋氧化物层，在衬底中形成隔离沟槽通过至少蚀刻到衬底上并且任选地进入衬底，在沟槽的暴露表面上形成介电隔离层，从沟槽的底部去除介电隔离层，并通过外延生长单晶硅形成隔离结构沟渠。

14. 发明授权

US5017999A Method for forming variable width isolation structures 失效
标题翻译：形成可变宽度隔离结构的方法
公开(公告)号：US5017999A
公开(公告)日：1991-05-21
申请号：US374960
申请日：1989-06-30
申请人： Roger L. Roisen , Curtis H. Rahn , John B. Straight , Michael S. Liu
发明人： Roger L. Roisen , Curtis H. Rahn , John B. Straight , Michael S. Liu
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L21/763
摘要： An isolation structure as well as a method for using and fabricating an isolation structure in an active layer deposited on a substrate the method of fabrication including the steps of forming a buried oxide layer in the active layer adjacent the substrate, forming an isolation trench in the active layer by etching at least up to and optionally into the substrate, forming a dielectric isolation layer on the exposed surfaces of the trench, removing the dielectric isolation layer from the bottom of the trench, and forming an isolation structure by epitaxially growing monocrystalline silicon in the trench.

15. 发明授权

US5008208A Method of making planarized, self-aligned bipolar integrated circuits 失效
标题翻译：制造平面化，自对准双极集成电路的方法
公开(公告)号：US5008208A
公开(公告)日：1991-04-16
申请号：US281195
申请日：1988-12-07
申请人： Michael S. Liu , Huang-Joung Chen
发明人： Michael S. Liu , Huang-Joung Chen
IPC分类号： H01L21/311 , H01L21/763
CPC分类号： H01L21/31111 , H01L21/763
摘要： A method for making a bipolar integrated circuit structure in a semiconductor substrate. A layer of insulating material having an implantation opening is formed on the upper surface of the semiconductor substrate. A polysilicon layer is formed in the implantation opening. A doping material is implanted into the polysilicon-filled opening. The doping material is diffused into the substrate material from the polysilicon-filled opening.
摘要翻译：一种在半导体衬底中制造双极集成电路结构的方法。在半导体衬底的上表面上形成具有注入开口的绝缘材料层。在植入口中形成多晶硅层。将掺杂材料注入到多晶硅填充的开口中。掺杂材料从多晶硅填充的开口扩散到衬底材料中。

16. 发明申请

US20090065866A1 Non-Planar Silicon-On-Insulator Device that Includes an "Area-Efficient" Body Tie 有权
标题翻译：包含“区域高效”身体领带的非平面矽绝缘体设备
公开(公告)号：US20090065866A1
公开(公告)日：2009-03-12
申请号：US11853611
申请日：2007-09-11
申请人： Bradley J. Larsen , Michael S. Liu , Paul S. Fechner
发明人： Bradley J. Larsen , Michael S. Liu , Paul S. Fechner
IPC分类号： H01L29/786
CPC分类号： H01L29/7853 , H01L29/66795 , H01L29/78615
摘要： Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric.
摘要翻译：公开了包括“面积效率”的身体搭接的非平面SOI器件。该器件包括体基片，形成在本体基片的表面上的绝缘体层，以及形成在绝缘体层的表面上的硅体。硅体优选地包括（i）连接源极区域和漏极区域的非平面沟道，以及（ii）与沟道相邻并且将沟道耦合到电压电位的主体连接。该器件还包括形成在沟道上的栅极电介质和形成在栅极电介质上的栅极材料。

17. 发明申请

US20080054360A1 Method and Apparatus for Regulating Photo Currents 有权
标题翻译：用于调节照片电流的方法和装置
公开(公告)号：US20080054360A1
公开(公告)日：2008-03-06
申请号：US11469803
申请日：2006-09-01
申请人： Harry HL Liu , Anuj Kohli , Michael S. Liu
发明人： Harry HL Liu , Anuj Kohli , Michael S. Liu
IPC分类号： H01L27/12
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for regulating photocurrents is described. A photocurrent regulator may include a transistor having an associated cross-sectional area. The photocurrent regulator is coupled between an integrated circuit and a voltage source. When a dose rate event occurs within the integrated circuit, the photocurrent regulator, via the cross-sectional area, regulates a recombination path to the voltage source. Consequently, photocurrents within the integrated circuit are regulated, preventing permanent damage within the integrated circuit.
摘要翻译：描述了用于调节光电流的方法和装置。光电流调节器可以包括具有相关横截面积的晶体管。光电流调节器耦合在集成电路和电压源之间。当在集成电路内发生剂量率事件时，光电流调节器通过横截面积调节到电压源的复合路径。因此，集成电路内的光电流被调节，防止集成电路内的永久性损坏。

18. 发明授权

US07322015B2 Simulating a dose rate event in a circuit design 有权
标题翻译：模拟电路设计中的剂量率事件
公开(公告)号：US07322015B2
公开(公告)日：2008-01-22
申请号：US11029308
申请日：2005-01-05
申请人： Harry H. L. Liu , Keith W. Golke , Eric E. Vogt , Michael S. Liu
发明人： Harry H. L. Liu , Keith W. Golke , Eric E. Vogt , Michael S. Liu
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5036
摘要： Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The subcircuit model can be in the form of a schematic-based representation or a netlist. The subcircuit model provides a model of a source junction and a drain junction in the transistor during the dose rate event. The subcircuit model also includes the size of the transistor being replaced and the dose rate of the dose rate event. Once the transistor is replaced with the subcircuit model, a dose rate simulation may be performed to determine the dose rate hardness of the circuit design.
摘要翻译：在剂量率事件期间晶体管的行为可以使用电路仿真软件包进行建模。子电路模型取代要仿真的电路设计中的晶体管。子电路模型可以是基于原理图的表示形式或网表。子电路模型在剂量率事件期间提供晶体管中的源极结和漏极结的模型。子电路模型还包括被替换的晶体管的尺寸和剂量率事件的剂量率。一旦晶体管被子电路模型替代，可以执行剂量率模拟来确定电路设计的剂量率硬度。

19. 发明授权

US4686758A Three-dimensional CMOS using selective epitaxial growth 失效
标题翻译：使用选择性外延生长的三维CMOS
公开(公告)号：US4686758A
公开(公告)日：1987-08-18
申请号：US815480
申请日：1986-01-02
申请人： Michael S. Liu , Bernd Hoefflinger
发明人： Michael S. Liu , Bernd Hoefflinger
IPC分类号： H01L21/20 , H01L21/822 , H01L29/78 , H01L27/02 , H01L29/04
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/8221
摘要： A three-dimensional CMOS integrated circuit structure in which two complementary field effect transistors are fabricated in vertical alignment with one another, and in which both transistors are single crystal and share a common crystal lattice structure and form a single unitary crystalline structure.
摘要翻译：三维CMOS集成电路结构，其中两个互补场效应晶体管彼此垂直对准地制造，并且其中两个晶体管是单晶并且共享共同的晶格结构并形成单一的单一晶体结构。

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