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11. 发明授权

US07713761B2 Doping apparatus, doping method, and method for fabricating thin film transistor 失效
标题翻译：掺杂装置，掺杂方法和制造薄膜晶体管的方法
公开(公告)号：US07713761B2
公开(公告)日：2010-05-11
申请号：US11798980
申请日：2007-05-18
申请人： Junichi Koezuka , Naoto Yamade
发明人： Junichi Koezuka , Naoto Yamade
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L22/24 , H01L27/12 , H01L27/1285 , H01L27/1292 , Y10S438/914
摘要： It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag.
摘要翻译：本发明的目的是提供一种掺杂装置，掺杂方法和制造薄膜晶体管的方法，所述薄膜晶体管可以对载流子浓度进行掺杂，这对于非破坏性地获得所需的电特性是最佳的一个简单的方式。根据本发明，通过使用接触角正确且精确地监测半导体元件的电特性（晶体管等中的阈值电压），并且通过控制掺杂方法来控制。此外，本发明可以通过原位监测特性而瞬间获取信息，并且可以在没有时间延迟的情况下反馈。

12. 发明授权

US07250312B2 Doping method and method for fabricating thin film transistor 有权
标题翻译：用于制造薄膜晶体管的掺杂方法和方法
公开(公告)号：US07250312B2
公开(公告)日：2007-07-31
申请号：US10910623
申请日：2004-08-04
申请人： Junichi Koezuka , Naoto Yamade
发明人： Junichi Koezuka , Naoto Yamade
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/24 , H01L27/12 , H01L27/1285 , H01L27/1292 , Y10S438/914
摘要： It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag.
摘要翻译：本发明的目的是提供一种掺杂装置，掺杂方法和制造薄膜晶体管的方法，所述薄膜晶体管可以对载流子浓度进行掺杂，这对于非破坏性地获得所需的电特性是最佳的一个简单的方式。根据本发明，通过使用接触角正确且精确地监测半导体元件的电特性（晶体管等中的阈值电压），并且通过控制掺杂方法来控制。此外，本发明可以通过原位监测特性而瞬间获取信息，并且可以在没有时间延迟的情况下反馈。

13. 发明授权

US09171938B2 Semiconductor element and method for manufacturing the same 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US09171938B2
公开(公告)日：2015-10-27
申请号：US12888835
申请日：2010-09-23
申请人： Shunpei Yamazaki , Junichiro Sakata , Akiharu Miyanaga , Masayuki Sakakura , Junichi Koezuka , Tetsunori Maruyama , Yuki Imoto
发明人： Shunpei Yamazaki , Junichiro Sakata , Akiharu Miyanaga , Masayuki Sakakura , Junichi Koezuka , Tetsunori Maruyama , Yuki Imoto
IPC分类号： H01L21/02 , H01L29/66 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66969 , H01L21/02565 , H01L27/1225 , H01L29/7869
摘要： An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.
摘要翻译：目的在于提供一种薄膜晶体管及其制造方法，该薄膜晶体管包括具有受控阈值电压，高操作速度，相对容易的制造工艺以及足够的可靠性的氧化物半导体。可以消除影响氧化物半导体层中的载流子浓度的杂质，例如氢原子或含有氢原子如H 2 O的化合物。可以与氧化物半导体层接触形成含有大量缺陷的氧化物绝缘层，例如悬挂键，使得杂质扩散到氧化物绝缘层中，并且氧化物半导体层中的杂质浓度降低。与氧化物半导体层接触的氧化物半导体层或氧化物绝缘层可以在使用低温泵抽真空的沉积室中形成，从而杂质浓度降低。

14. 发明授权

US08847233B2 Semiconductor device having a trenched insulating layer coated with an oxide semiconductor film 有权
标题翻译：具有涂覆有氧化物半导体膜的沟槽绝缘层的半导体器件
公开(公告)号：US08847233B2
公开(公告)日：2014-09-30
申请号：US13463092
申请日：2012-05-03
申请人： Atsuo Isobe , Toshinari Sasaki , Junichi Koezuka , Shunpei Yamazaki
发明人： Atsuo Isobe , Toshinari Sasaki , Junichi Koezuka , Shunpei Yamazaki
IPC分类号： H01L29/04 , H01L29/10 , H01L31/036 , H01L31/0376 , H01L31/20 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392 , H01L27/108 , H01L21/84 , H01L49/02 , H01L21/425 , H01L29/66 , H01L29/786 , H01L27/115
CPC分类号： H01L29/4238 , H01L21/02565 , H01L21/265 , H01L21/425 , H01L21/84 , H01L27/1085 , H01L27/10876 , H01L27/1156 , H01L27/1203 , H01L27/1225 , H01L28/40 , H01L29/045 , H01L29/0847 , H01L29/66477 , H01L29/66742 , H01L29/66969 , H01L29/78603 , H01L29/7869 , H01L29/78693
摘要： It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.
摘要翻译：本发明的目的是提供一种抑制短路效应并实现小型化的半导体器件及其制造方法。在绝缘层中形成沟槽，并且将杂质添加到与沟槽的上端角部接触的氧化物半导体膜，由此形成源极区域和漏极区域。利用上述结构，可以实现小型化。此外，利用沟槽，即使当源电极层和漏电极层之间的距离缩短时，也可以适当地抑制沟槽的深度适当地设定短沟道效应。

15. 发明授权

US08716073B2 Method for processing oxide semiconductor film and method for manufacturing semiconductor device 有权
标题翻译：氧化物半导体膜的制造方法及半导体装置的制造方法
公开(公告)号：US08716073B2
公开(公告)日：2014-05-06
申请号：US13547451
申请日：2012-07-12
申请人： Shunpei Yamazaki , Shinji Ohno , Yuichi Sato , Junichi Koezuka , Sachiaki Tezuka
发明人： Shunpei Yamazaki , Shinji Ohno , Yuichi Sato , Junichi Koezuka , Sachiaki Tezuka
IPC分类号： H01L21/336
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02664 , H01L27/1225
摘要： To provide an oxide semiconductor film including a low-resistance region, which can be applied to a transistor. To provide a transistor including the oxide semiconductor film, which can perform at high speed. To provide a high-performance semiconductor device including the transistor including the oxide semiconductor film, which can perform at high speed, with high yield. A film having a reducing property is formed over the oxide semiconductor film. Next, part of oxygen atoms are transferred from the oxide semiconductor film to the film having a reducing property. Next, an impurity is added to the oxide semiconductor film through the film having a reducing property and then, the film having a reducing property is removed, so that a low-resistance region is formed in the oxide semiconductor film.
摘要翻译：提供一种可以应用于晶体管的包含低电阻区域的氧化物半导体膜。提供可以高速执行的包括氧化物半导体膜的晶体管。提供一种高性能半导体器件，其包括能够以高产率高速执行的包括氧化物半导体膜的晶体管。在氧化物半导体膜上形成具有还原性的膜。接下来，氧原子的一部分从氧化物半导体膜转移到具有还原性的膜。接下来，通过具有还原性的膜向氧化物半导体膜添加杂质，然后去除具有还原性的膜，从而在氧化物半导体膜中形成低电阻区域。

16. 发明授权

US08629030B2 Method for manufacturing SOI substrate 有权
公开(公告)号：US08629030B2
公开(公告)日：2014-01-14
申请号：US13411864
申请日：2012-03-05
申请人： Takeshi Shichi , Junichi Koezuka , Hideto Ohnuma , Shunpei Yamazaki
发明人： Takeshi Shichi , Junichi Koezuka , Hideto Ohnuma , Shunpei Yamazaki
IPC分类号： H01L21/33 , H01L21/8222
摘要： The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween.

17. 发明申请

US20120276690A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120276690A1
公开(公告)日：2012-11-01
申请号：US13549540
申请日：2012-07-16
申请人： Keiichi SEKIGUCHI , Junichi Koezuka , Yasuyuki Arai , Shunpei Yamazaki
发明人： Keiichi SEKIGUCHI , Junichi Koezuka , Yasuyuki Arai , Shunpei Yamazaki
IPC分类号： H01L21/336 , H01L21/50
CPC分类号： H01L27/1214 , H01L27/1203 , H01L27/127 , H01L29/78624 , H01L29/78645 , H01L29/78675 , H01L29/78696 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05548 , H01L2224/05569 , H01L2224/05572 , H01L2224/16225 , H01L2224/48091 , H01L2224/73265 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film therebetween is provided; an impurity is added to a part of a first region overlapped with the gate electrode with the gate insulating film therebetween in the active layer and a second region but the first region in the active layer by adding the impurity to the active layer from one oblique direction; and the second region is situated in the one direction relative to the first region.
摘要翻译：本发明提供了一种制造半导体器件的方法，通过该方法，提供了包括有源层，与有源层接触的栅极绝缘膜和与有源层重叠的栅极与其间的栅极绝缘膜的晶体管。在有源层和第二区域之间，与栅电极重叠的第一区域的一部分添加杂质，而通过从有源层向一个倾斜方向添加杂质，而在有源层中添加杂质 ; 并且第二区域相对于第一区域位于一个方向上。

18. 发明授权

US07851332B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07851332B2
公开(公告)日：2010-12-14
申请号：US12237606
申请日：2008-09-25
申请人： Shunpei Yamazaki , Junichi Koezuka , Tetsuya Kakehata
发明人： Shunpei Yamazaki , Junichi Koezuka , Tetsuya Kakehata
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/42384 , H01L29/66772 , H01L29/78621
摘要： A semiconductor device including a semiconductor substrate is provided. The semiconductor substrate includes a substrate having an insulating surface, and a plurality of stacks over the substrate having an insulating surface. Each of the plurality of stacks includes a bonding layer over the substrate having an insulating surface, an insulating layer over the bonding layer, and a single crystal semiconductor layer over the insulating layer. The substrate having an insulating surface has a depression, and the depression is provided between one of the plurality of stacks and another adjacent one of the plurality of stacks.
摘要翻译：提供了包括半导体衬底的半导体器件。半导体衬底包括具有绝缘表面的衬底和在衬底上的多个堆叠，其具有绝缘表面。多个堆叠中的每一个在基板上包括具有绝缘表面的接合层，接合层上的绝缘层以及绝缘层上的单晶半导体层。具有绝缘表面的基板具有凹陷，并且凹陷设置在多个叠层中的一个和多个叠层中的另一个相邻的堆叠之间。

19. 发明授权

US07501671B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US07501671B2
公开(公告)日：2009-03-10
申请号：US11729241
申请日：2007-03-28
申请人： Takashi Hamada , Satoshi Murakami , Shunpei Yamazaki , Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Toru Takayama
发明人： Takashi Hamada , Satoshi Murakami , Shunpei Yamazaki , Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Toru Takayama
IPC分类号： H01L27/148 , H01L29/74 , H01L29/768
CPC分类号： H01L21/02672 , G02F1/13454 , H01L21/2022 , H01L21/3226 , H01L27/12 , H01L27/1248 , H01L27/1277 , H01L27/1288 , H01L27/3246 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/66765 , H01L29/78621 , H01L51/5253 , H01L51/56
摘要： The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semiconductor film to the semiconductor film containing a rare gas element by a heat treatment. Furthermore, a first impurity region and a second impurity region formed in a semiconductor layer of a first n-channel TFT are provided outside a gate electrode. A third impurity region formed in a semiconductor layer of a second n-channel TFT is provided so as to be partially overlapped with a gate electrode. A third impurity region is provided outside a gate electrode. A fourth impurity region formed in a semiconductor layer of a p-channel TFT is provided so as to be partially overlapped with a gate electrode. A fifth impurity region is provided outside a gate electrode.

20. 发明申请

US20070187761A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070187761A1
公开(公告)日：2007-08-16
申请号：US11729241
申请日：2007-03-28
申请人： Takashi Hamada , Satoshi Murakami , Shunpei Yamazaki , Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Toru Takayama
发明人： Takashi Hamada , Satoshi Murakami , Shunpei Yamazaki , Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Toru Takayama
IPC分类号： H01L27/12
CPC分类号： H01L21/02672 , G02F1/13454 , H01L21/2022 , H01L21/3226 , H01L27/12 , H01L27/1248 , H01L27/1277 , H01L27/1288 , H01L27/3246 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/66765 , H01L29/78621 , H01L51/5253 , H01L51/56
摘要： The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semiconductor film to the semiconductor film containing a rare gas element by a heat treatment. Furthermore, a first impurity region and a second impurity region formed in a semiconductor layer of a first n-channel TFT are provided outside a gate electrode. A third impurity region formed in a semiconductor layer of a second n-channel TFT is provided so as to be partially overlapped with a gate electrode. A third impurity region is provided outside a gate electrode. A fourth impurity region formed in a semiconductor layer of a p-channel TFT is provided so as to be partially overlapped with a gate electrode. A fifth impurity region is provided outside a gate electrode.
摘要翻译：本发明的特征在于，在通过阻挡层使用催化元件而获得的结晶半导体膜上形成含有稀有气体元素的半导体膜，催化元素从结晶半导体膜移动到含有稀有气体元素通过热处理。此外，形成在第一n沟道TFT的半导体层中的第一杂质区域和第二杂质区域设置在栅电极的外侧。形成在第二n沟道TFT的半导体层中的第三杂质区域设置成与栅电极部分重叠。第三杂质区域设置在栅极外部。形成在p沟道TFT的半导体层中的第四杂质区域设置成与栅电极部分重叠。第五杂质区域设置在栅极外部。

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