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11. 发明授权

US07214581B2 Method of fabricating flash memory device 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US07214581B2
公开(公告)日：2007-05-08
申请号：US11019300
申请日：2004-12-23
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention provides a method of fabricating a flash memory device, in which floating gates in neighbor cells are separated from each other without using photolithography, which enhances electrical characteristics of the device, and which facilitates a cell size reduction. The present invention includes forming a mask defining a trench forming area on a semiconductor substrate, forming a trench in the semiconductor layer by removing a portion of the semiconductor layer using the mask, forming a device isolation layer filling up the trench to maintain an effective isolation layer thickness exceeding a predefined thickness, removing the mask, forming a conductor layer over the substrate including the device isolation layer, planarizing the conductor layer and the device isolation layer to lie in a same plane, and forming an insulating layer over the substrate including the conductor patterns.
摘要翻译：本发明提供一种制造闪存器件的方法，其中相邻单元中的浮置栅极彼此分离而不使用光刻，这增强了器件的电气特性，并且有助于电池尺寸减小。本发明包括在半导体衬底上形成限定沟槽形成区域的掩模，通过使用掩模去除半导体层的一部分，在半导体层中形成沟槽，形成填充沟槽的器件隔离层以保持有效隔离层厚度超过预定厚度，去除掩模，在包括器件隔离层的衬底上形成导体层，将导体层和器件隔离层平坦化在同一平面上，并在衬底上形成绝缘层，包括导体图案。

12. 发明授权

US07041555B2 Method for manufacturing flash memory device 有权
标题翻译：闪存器件制造方法
公开(公告)号：US07041555B2
公开(公告)日：2006-05-09
申请号：US10883279
申请日：2004-06-30
申请人： Jung Ryul Ahn , Jum Soo Kim
发明人： Jung Ryul Ahn , Jum Soo Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Disclosed is a method for manufacturing a flash memory device. In a process of forming a flash memory cell and a select transistor through a process of forming a polysilicon layer for a floating gate, a process of forming a dielectric layer and a process of forming a polysilicon layer for a control gate, the dielectric layer is formed and the dielectric layer in a region where a select transistor will be formed is then removed, thereby forming a select gate line in which the polysilicon layer for the floating gate and the polysilicon layer for the control gate are electrically connected. Furthermore, in a process of forming a flash memory cell and a select transistor through a process of forming a polysilicon layer for a floating gate, a process of forming a dielectric layer and a process of forming a polysilicon layer for a control gate, forming an interlayer insulating layer on the entire structure and then forming a contact, the dielectric layer on the polysilicon layer for the floating gate in a region where a select transistor will be formed and the polysilicon layer for the control gate are all removed whereby the polysilicon layer for the floating gate and a contact plug are directly electrically connected.
摘要翻译：公开了一种用于制造闪速存储器件的方法。在通过形成用于浮置栅极的多晶硅层的工艺，形成介电层的工艺和形成用于控制栅极的多晶硅层的工艺来形成闪存单元和选择晶体管的过程中，介电层是然后去除形成选择晶体管的区域中的电介质层，从而形成选择栅极线，其中浮栅的多晶硅层和用于控制栅的多晶硅层电连接。此外，在通过形成用于浮置栅极的多晶硅层的工艺来形成闪存单元和选择晶体管的过程中，形成介电层的工艺和形成用于控制栅极的多晶硅层的工艺，形成层间绝缘层，然后形成接触，在形成选择晶体管的区域中的浮栅的多晶硅层上的电介质层和用于控制栅极的多晶硅层全部被去除，由此用于浮动栅极和接触插头直接电连接。

13. 发明授权

US06627105B1 Method of fabricating a piezoelectric ceramic 失效
标题翻译：制造压电陶瓷的方法
公开(公告)号：US06627105B1
公开(公告)日：2003-09-30
申请号：US09722110
申请日：2000-11-27
申请人： Tae Kyu Kim , Jum Soo Kim , Mun Hwa Lee , Jong Woo Kim
发明人： Tae Kyu Kim , Jum Soo Kim , Mun Hwa Lee , Jong Woo Kim
IPC分类号： C04B35491
CPC分类号： C01G25/006 , C01P2002/72 , C04B35/491 , C04B2235/3249 , C04B2235/3251 , C04B2235/3296 , C04B2235/449 , C04B2235/5204 , H01L41/187
摘要： There is disclosed a method of fabricating a piezoelectric ceramics. It can obtain a small grain size and a fine grain phase by forming a combined powder being major components, stirring the combined powder with (COOH)2 water solution, dropping a Pb(NO3)2 water solution into the stirred powder, and forming a PZT powder by calcinations and sintering processes.
摘要翻译：公开了一种制造压电陶瓷的方法。通过形成作为主要成分的组合粉末，用（COOH）2水溶液搅拌合并的粉末，将Pb（NO 3）2水溶液滴入搅拌粉末中，可以获得小粒径和细晶粒相，并形成 PZT粉末通过煅烧和烧结过程。

14. 发明申请

US20100295133A1 Resistor of Semiconductor Device and Method of Forming the Same 审中-公开
标题翻译：半导体器件的电阻及其形成方法
公开(公告)号：US20100295133A1
公开(公告)日：2010-11-25
申请号：US12773295
申请日：2010-05-04
申请人： Jum Soo Kim
发明人： Jum Soo Kim
IPC分类号： H01L27/105 , H01L21/02
CPC分类号： H01L28/20 , H01L27/11526 , H01L27/11531
摘要： The resistor of a semiconductor device comprises a semiconductor substrate comprising isolation layers and active regions, a gate insulating layer and a first polysilicon layer formed over the active region, a second polysilicon layer separated into a first pattern formed on the isolation layer, and a second pattern formed over the first polysilicon layer and higher than the first pattern, a first interlayer dielectric layer covering the first pattern over the isolation layer, a second interlayer dielectric layer formed over the first interlayer dielectric layer, contact holes exposing the first pattern in the first and second interlayer dielectric layers, and contact plugs filling the respective contact holes and coupled to the first pattern.
摘要翻译：半导体器件的电阻器包括半导体衬底，其包括隔离层和有源区，栅极绝缘层和形成在有源区上的第一多晶硅层，分离成形成在隔离层上的第一图案的第二多晶硅层，以及第二图案形成在第一多晶硅层上并高于第一图案，覆盖隔离层上的第一图案的第一层间电介质层，形成在第一层间电介质层上的第二层间电介质层，在第一多晶硅层中形成的第一图案的接触孔和第二层间电介质层，以及填充相应接触孔并与第一图案耦合的接触塞。

15. 发明授权

US07715230B2 Method of operating a flash memory device 有权
标题翻译：操作闪存设备的方法
公开(公告)号：US07715230B2
公开(公告)日：2010-05-11
申请号：US12146927
申请日：2008-06-26
申请人： Jum Soo Kim , Tae Gyun Kim
发明人： Jum Soo Kim , Tae Gyun Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3454
摘要： A method of operating a flash memory device wherein the width of threshold voltage distribution of memory cells is adjusted by setting different conditions of a program operation in accordance with levels of threshold voltages of the memory cells. As a result, width of the threshold voltage distribution of memory cells may be narrowed.
摘要翻译：一种操作闪存器件的方法，其中通过根据存储器单元的阈值电压的电平设置程序操作的不同条件来调节存储器单元的阈值电压分布的宽度。结果，存储单元的阈值电压分布的宽度可能变窄。

16. 发明授权

US07553724B2 Method for manufacturing code address memory cell by which a stack insulating film of an oxide film and a nitride film used as a dielectric film in a flash memory is used as a gate oxide film 有权
标题翻译：用于制造代码地址存储单元的方法，其中使用氧化膜的叠层绝缘膜和用作闪速存储器中的电介质膜的氮化物膜作为栅氧化膜
公开(公告)号：US07553724B2
公开(公告)日：2009-06-30
申请号：US10029394
申请日：2001-12-28
申请人： Jum Soo Kim , Sung Mun Jung , Min Kuck Cho , Young Bok Lee
发明人： Jum Soo Kim , Sung Mun Jung , Min Kuck Cho , Young Bok Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/792
摘要： The present invention relates to a method manufacturing a code address memory (CAM) cell. The present invention uses a dielectric film in which an oxide film and a nitride film between a floating gate and a control gate in a flash memory cell are stacked as a gate insulating film between a semiconductor substrate and a gate in the CAM cell. Therefore, the present invention can reduce the area of a peripheral circuit region and stably secure repaired data since the CAM cell can be stably driven at a low operating voltage and additional boosting circuit is thus not required.
摘要翻译：本发明涉及制造代码地址存储器（CAM）单元的方法。本发明使用其中在闪存单元中的浮栅和控制栅之间的氧化物膜和氮化物膜作为栅极绝缘膜堆叠在CAM单元中的半导体衬底和栅极之间的电介质膜。因此，本发明可以减小外围电路区域的面积并稳定地确保修复数据，因为可以在低工作电压下稳定地驱动CAM单元，因此不需要附加的升压电路。

17. 发明申请

US20070155124A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070155124A1
公开(公告)日：2007-07-05
申请号：US11593868
申请日：2006-11-07
申请人： Jung Ryul Ahn , Jum Soo Kim
发明人： Jung Ryul Ahn , Jum Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L27/1052
摘要： A method of manufacturing a semiconductor device wherein a gate insulating layer and a polysilicon layer are formed over a semiconductor substrate in which a cell region and a peri region are defined. Portions of the polysilicon layer, the gate insulating layer, and the semiconductor substrate of the peri region are etched to form a first trench in the peri region. A first insulating layer is formed on the entire surface so that the first trench is gap filled. Portions of the first insulating layer, the first polysilicon layer, the gate insulating layer, and the semiconductor substrate of the cell region are etched to form second trenches in the cell region. A sidewall oxide layer and a nitride layer are formed within the second trenches, so that the sidewall oxide layer and the nitride layer are laminated. The second trenches are gap-filled with a second insulating layer to form isolation layers. Since plasma attack and the infiltration of hydrogen (H2) can be prevented, the malfunction of a cell and peripheral circuits can be prevented.
摘要翻译：一种半导体器件的制造方法，其中在限定了单元区域和周边区域的半导体衬底上形成栅极绝缘层和多晶硅层。蚀刻多晶硅层的一部分，栅极绝缘层和半导体衬底，以在周边区域形成第一沟槽。在整个表面上形成第一绝缘层，使得第一沟槽间隙填充。蚀刻单元区域的第一绝缘层，第一多晶硅层，栅极绝缘层和半导体衬底的部分，以在单元区域中形成第二沟槽。在第二沟槽内形成侧壁氧化物层和氮化物层，从而层叠侧壁氧化物层和氮化物层。第二沟槽间隙填充有第二绝缘层以形成隔离层。由于可以防止等离子体侵蚀和氢（H 2 2）的渗透，所以可以防止电池和外围电路的故障。

18. 发明授权

US07015099B2 Method of manufacturing a flash memory cell capable of increasing a coupling ratio 失效
标题翻译：制造能够提高耦合比的闪存单元的方法
公开(公告)号：US07015099B2
公开(公告)日：2006-03-21
申请号：US11004301
申请日：2004-12-03
申请人： Jum Soo Kim , Sung Mun Jung , Jung Ryul Ahn , Young Ki Shin , Young Bok Lee
发明人： Jum Soo Kim , Sung Mun Jung , Jung Ryul Ahn , Young Ki Shin , Young Bok Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76235
摘要： A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for burying a trench to etch the trench insulating film to a desired space. Therefore, it is possible to secure the coupling ratio of a floating gate by maximum and implement a device of a smaller size.
摘要翻译：一种制造闪存单元的方法。该方法包括控制在形成用于埋入沟槽的沟槽绝缘膜的工艺之前/之后执行的沟槽绝缘膜的壁牺牲氧化过程，壁氧化过程和清洁过程，以将沟槽绝缘膜蚀刻到期望的空间。因此，可以最大限度地确保浮动栅极的耦合比，并且实现更小尺寸的器件。

19. 发明授权

US06720217B2 Method of manufacturing flash memory device using trench device isolation process 失效
标题翻译：使用沟槽器件隔离工艺制造闪存器件的方法
公开(公告)号：US06720217B2
公开(公告)日：2004-04-13
申请号：US10329696
申请日：2002-12-27
申请人： Jum Soo Kim , Sung Mun Jung
发明人： Jum Soo Kim , Sung Mun Jung
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76232 , H01L27/115
摘要： The present invention relates to a method of manufacturing a flash memory device. The method comprises the steps of sequentially depositing a pad oxide film and a pad nitride film on a semiconductor substrate, when trenches are formed by etching the pad nitride film, the pad oxide film and the substrate using a mask for forming a device isolation film, forming trenches having a different depth in a cell region and in a peripheral by controlling an etch angle and etch target depending on the width of the trench, depositing trench insulating films on the entire surfaces to bury the trenches with the trench insulating films, performing a chemical mechanical polishing process and a strip process for the trench insulating films to form the trench insulating film upper structures of which are protruded, forming a well region through an ion implantation process, and forming a tunnel oxide film, a floating gate, a dielectric film and a control gate. Therefore, as a cell source resistance is reduced, a back-bias effect generating due to the source resistance can be prevented. As the cell current is increased, the read speed of the device can be increased.
摘要翻译：本发明涉及一种制造闪速存储器件的方法。该方法包括以下步骤：当通过使用用于形成器件隔离膜的掩模蚀刻衬垫氮化物膜，衬垫氧化物膜和衬底形成沟槽时，在半导体衬底上顺序地沉积焊盘氧化物膜和衬垫氮化物膜，通过根据沟槽的宽度控制蚀刻角度和蚀刻目标，在单元区域和周边中形成具有不同深度的沟槽，在整个表面上沉积沟槽绝缘膜，以用沟槽绝缘膜掩埋沟槽，执行化学机械抛光工艺和用于沟槽绝缘膜的剥离工艺，以形成沟槽绝缘膜上部结构突出，通过离子注入工艺形成阱区，并形成隧道氧化膜，浮栅，电介质膜和控制门。因此，随着电池源电阻降低，可以防止由于源电阻而产生的反偏压效应。随着电池电流的增加，可以提高器件的读取速度。

20. 发明授权

US06620684B2 Method of manufacturing nonvolatile memory cell 有权
公开(公告)号：US06620684B2
公开(公告)日：2003-09-16
申请号：US10029391
申请日：2001-12-28
申请人： Jum Soo Kim , Sung Mun Jung , Sang Bum Lee , Min Kuck Cho , Young Bok Lee
发明人： Jum Soo Kim , Sung Mun Jung , Sang Bum Lee , Min Kuck Cho , Young Bok Lee
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/6656
摘要： The present invention relates to a method of manufacturing a nonvolatile memory cell. The present invention uses tungsten (W) as an upper layer of a control gate electrode in order to integrate the memory cell and performs an ion implantation process for forming a source region and a drain region before a selective oxidization process that is performed to prevent abnormal oxidization of tungsten (W). Therefore, the present invention can reduce a RC delay time of word lines depending on integration of the memory cell and also secure a given distance between a silicon substrate and a tunnel oxide film. As a result, the present invention can solve a data retention problem of the flash memory.

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