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11. 发明授权

US07106617B2 Ferroelectric memory devices having a plate line control circuit and methods for operating the same 失效
公开(公告)号：US07106617B2
公开(公告)日：2006-09-12
申请号：US11029616
申请日：2005-01-05
申请人： Byung-Gil Jeon , Ki-nam Kim
发明人： Byung-Gil Jeon , Ki-nam Kim
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

12. 发明授权

US06953959B2 Integrated circuit devices including self-aligned contacts with increased alignment margin 有权
标题翻译：集成电路器件包括具有增加的对准裕度的自对准触点
公开(公告)号：US06953959B2
公开(公告)日：2005-10-11
申请号：US10156477
申请日：2002-05-28
申请人： Won-suk Yang , Ki-nam Kim
发明人： Won-suk Yang , Ki-nam Kim
IPC分类号： H01L21/768 , H01L21/60 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/00
CPC分类号： H01L21/76897
摘要： An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions. A plurality of bit line structures are on the substrate, extending transverse to the word line structures and contacting the second conductive pads. Related methods of fabrication are also described.
摘要翻译：诸如存储器件的集成电路器件包括衬底以及衬底中的多行有源区域，有源区域以交错图案排列，使得第一行的有源区域与隔离的部分对准分隔相邻第二行的有效区域的区域。源极和漏极区域处于有源区域中并且被布置成使得每个有源区域包括设置在两个源极区域之间的漏极区域。多个字线结构位于衬底上，横向于有源区的行布置，使得字线结构跨越源极区域和漏极区域之间的有源区域。导电焊盘的相应行设置在相应的相邻字线结构之间，包括源区上的第一导电焊盘，漏极区上的第二导电焊盘以及分离有源区的隔离区上的第三导电。多个位线结构在基板上，横向于字线结构延伸并与第二导电焊盘接触。还描述了相关的制造方法。

13. 发明授权

US06836019B2 Semiconductor device having multilayer interconnection structure and manufacturing method thereof 有权
标题翻译：具有多层互连结构的半导体器件及其制造方法
公开(公告)号：US06836019B2
公开(公告)日：2004-12-28
申请号：US09999104
申请日：2001-10-31
申请人： Won-suk Yang , Ki-nam Kim , Hong-sik Jeong
发明人： Won-suk Yang , Ki-nam Kim , Hong-sik Jeong
IPC分类号： H01L2348
CPC分类号： H01L23/485 , H01L21/76801 , H01L21/76804 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a line width of an entrance portion adjacent to the surface of the ILD layer larger than the line width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a line width larger than that of the second contact stud. The second contact stud has a line width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad. The entrance portion of the first contact stud has a line width about 30-60% larger than that of the contacting portion.
摘要翻译：半导体器件及其制造方法包括半导体衬底，在半导体衬底上形成的层间电介质层（ILD）层，形成在ILD层中的第一接触柱，具有与ILD的表面相邻的入口部的线宽度大于与半导体衬底相邻的接触部分的线宽度的第二接触柱，以及形成在ILD层中的与第一接触柱隔开的第二接触柱。半导体器件还包括形成在ILD层上的接合焊盘，其接触第二接触柱的表面，其线宽大于第二接触柱的线宽。第二接触螺柱具有与入口部分相同的接触部分的线宽度。此外，在着陆焊盘的侧壁上形成至少一个包括蚀刻阻挡材料的间隔物，并且在着陆焊盘上形成蚀刻停止层。第一接触柱的入口部分具有比接触部分的线宽大30-60％的线宽。

14. 发明授权

US5705440A Methods of fabricating integrated circuit field effect transistors having reduced-area device isolation regions 失效
标题翻译：制造具有减小面积的器件隔离区域的集成电路场效应晶体管的方法
公开(公告)号：US5705440A
公开(公告)日：1998-01-06
申请号：US681875
申请日：1996-07-29
申请人： Byung-hyug Roh , Ki-nam Kim
发明人： Byung-hyug Roh , Ki-nam Kim
IPC分类号： H01L21/76 , H01L21/336 , H01L29/08 , H01L29/417 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66636 , H01L29/0847 , H01L29/41766 , H01L29/7834
摘要： A integrated circuit field effect transistor is formed with device isolation regions disposed on opposite sides of the transistor, each of which include a shallow insulation-filled trench region which abuts an insulating region underlying an active region of the transistor. A pair of spaced apart insulation-filled trench regions are formed in a semiconductor substrate at a surface of the substrate. An insulated gate is formed on the substrate between and separated from the insulation-filled trench regions. Spaced apart source and drain insulating regions are formed in the substrate, a respective one of which is disposed between the insulated gate and a respective one of the insulation-filled trench regions. Corresponding spaced apart source and drain regions are then formed on the spaced apart source and drain insulating regions. The insulated gate is formed overlying a channel region disposed between lightly doped source and drain regions.
摘要翻译：形成集成电路场效应晶体管，其中器件隔离区域设置在晶体管的相对侧上，其中每一个包括与晶体管的有源区下面的绝缘区相邻的浅绝缘填充沟槽区。在衬底的表面上的半导体衬底中形成一对间隔开的绝缘填充沟槽区域。绝缘栅极形成在衬底上并且与绝缘填充的沟槽区域分离。间隔开的源极和漏极绝缘区域形成在衬底中，其相应的一个设置在绝缘栅极和相应的绝缘填充沟槽区域之间。然后在间隔开的源极和漏极绝缘区域上形成相应的间隔开的源极和漏极区域。绝缘栅极形成在布置在轻掺杂源极和漏极区域之间的沟道区域上。

15. 发明申请

US20110133063A1 Optical waveguide and coupler apparatus and method of manufacturing the same 有权
标题翻译：光波导和耦合器装置及其制造方法
公开(公告)号：US20110133063A1
公开(公告)日：2011-06-09
申请号：US12911415
申请日：2010-10-25
申请人： Ho-chul Ji , Ki-nam Kim , Yong-woo Hyung , Kyoung-won Na , Kyoung-ho Ha , Yoon-dong Park , Dae-lok Bae , Jin-kwon Bok , Pil-kyu Kang , Sung-dong Suh , Seong-gu Kim , Dong-jae Shin , In-sung Joe
发明人： Ho-chul Ji , Ki-nam Kim , Yong-woo Hyung , Kyoung-won Na , Kyoung-ho Ha , Yoon-dong Park , Dae-lok Bae , Jin-kwon Bok , Pil-kyu Kang , Sung-dong Suh , Seong-gu Kim , Dong-jae Shin , In-sung Joe
IPC分类号： G02B6/42 , G02B6/02 , G02B6/34 , G02B6/26 , H01L31/12
CPC分类号： G02B6/124 , G02B6/122 , G02B6/30 , G02B6/34 , G02B6/4214 , G02B2006/12104
摘要： Optical waveguide and coupler devices and methods include a trench formed in a bulk semiconductor substrate, for example, a bulk silicon substrate. A bottom cladding layer is formed in the trench, and a core region is formed on the bottom cladding layer. A reflective element, such as a distributed Bragg reflector can be formed under the coupler device and/or the waveguide device. Because the optical devices are integrated in a bulk substrate, they can be readily integrated with other devices on a chip or die in accordance with silicon photonics technology. Specifically, for example, the optical devices can be integrated in a DRAM memory circuit chip die.
摘要翻译：光波导和耦合器器件和方法包括形成在体半导体衬底中的沟槽，例如体硅衬底。在沟槽中形成底层，在底面包层上形成芯部区域。可以在耦合器装置和/或波导装置下形成反射元件，例如分布式布拉格反射器。因为光学器件集成在大容量衬底中，所以它们可以根据硅光子学技术容易地与芯片上或芯片上的其它器件集成。具体地，例如，光学器件可以集成在DRAM存储器电路芯片芯片中。

16. 发明授权

US07348616B2 Ferroelectric integrated circuit devices having an oxygen penetration path 失效
标题翻译：具有氧气穿透路径的铁电集成电路器件
公开(公告)号：US07348616B2
公开(公告)日：2008-03-25
申请号：US11248629
申请日：2005-10-12
申请人： Heung-jin Joo , Ki-nam Kim , Yoon-jong Song
发明人： Heung-jin Joo , Ki-nam Kim , Yoon-jong Song
IPC分类号： H01L29/76
CPC分类号： H01L28/55 , H01L27/11502 , H01L27/11507 , H01L28/57
摘要： Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.
摘要翻译：诸如存储器件的铁电集成电路器件形成在集成电路衬底上。铁电电容器在集成电路衬底上，并且集成电路衬底上的另一结构覆盖至少一部分铁电电容器。所述另外的结构包括至少一层，以提供对所述铁电电容器的氧气流的阻挡。与强电介质电容器接触的氧气穿透路径介于铁电电容器和另外的结构之间。提供氧流阻挡的层可以是封装的阻挡层。还提供了用于形成诸如存储器件的铁电集成电路器件的方法。

17. 发明申请

US20060256607A1 Ferroelectric memory devices having a plate line control circuit 失效
标题翻译：具有板线控制电路的铁电存储器件
公开(公告)号：US20060256607A1
公开(公告)日：2006-11-16
申请号：US11491872
申请日：2006-07-24
申请人： Byung-Gil Jeon , Ki-nam Kim
发明人： Byung-Gil Jeon , Ki-nam Kim
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.
摘要翻译：铁电存储器件包括铁电存储器单元。铁电存储单元具有至少一个位线和板线。控制电路在写入操作期间与写入线的激活基本同时地驱动具有写入数据的至少一个位线。存储器件还可以包括耦合到铁电存储单元的读出放大器，并且控制电路还可以被配置为在读取操作期间与读出放大器的激活基本同时地去激活平板线。

18. 发明授权

US06979881B2 Ferroelectric integrated circuit devices having an oxygen penetration path 失效
标题翻译：具有氧气穿透路径的铁电集成电路器件
公开(公告)号：US06979881B2
公开(公告)日：2005-12-27
申请号：US10308843
申请日：2002-12-03
申请人： Heung-jin Joo , Ki-nam Kim , Yoon-jong Song
发明人： Heung-jin Joo , Ki-nam Kim , Yoon-jong Song
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L27/115 , H01L29/92
CPC分类号： H01L28/55 , H01L27/11502 , H01L27/11507 , H01L28/57
摘要： Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the Ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.
摘要翻译：诸如存储器件的铁电集成电路器件形成在集成电路衬底上。铁电电容器在集成电路基板上，并且集成电路基板上的另外的结构覆盖在铁电电容器的至少一部分上。所述另外的结构包括至少一层，以提供对所述铁电电容器的氧气流的阻挡。与强电介质电容器接触的氧气穿透路径介于铁电电容器和另外的结构之间。提供氧流阻挡的层可以是封装的阻挡层。还提供了用于形成诸如存储器件的铁电集成电路器件的方法。

19. 发明授权

US06969658B2 Methods providing oxide layers having reduced thicknesses at central portions thereof 失效
标题翻译：提供在其中心部分具有减小的厚度的氧化物层的方法
公开(公告)号：US06969658B2
公开(公告)日：2005-11-29
申请号：US10173373
申请日：2002-06-17
申请人： Chang-hyun Cho , Min-hee Cho , Ki-nam Kim
发明人： Chang-hyun Cho , Min-hee Cho , Ki-nam Kim
IPC分类号： H01L21/28 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/423
CPC分类号： H01L21/28176 , H01L21/28167 , H01L21/823462 , H01L21/823481 , H01L29/42368
摘要： Methods of forming an integrated circuit device may include forming first and second spaced apart source/drain regions on a surface of a semiconductor substrate. A gate insulating layer can be formed on the semiconductor substrate extending between the first and second spaced apart souce/drain regions. The gate insulating layer can have a reduced thickness at a central portion thereof between the first and second spaced apart source/drain regions. A thickness of the gate insulating layer can increase as it extends toward each of the source/drain regions. A gate electrode can be formed on the gate insulating layer such that the gate insulating layer is between the semiconductor substrate and the gate electrode. Related devices are also discussed.
摘要翻译：形成集成电路器件的方法可以包括在半导体衬底的表面上形成第一和第二间隔开的源极/漏极区域。可以在半导体衬底上形成栅极绝缘层，该半导体衬底在第一和第二间隔开的漏极/漏极区域之间延伸。栅极绝缘层在其第一和第二间隔开的源极/漏极区域的中心部分可以具有减小的厚度。栅极绝缘层的厚度可以随着朝向每个源/漏区延伸而增加。栅电极可以形成在栅极绝缘层上，使得栅极绝缘层位于半导体衬底和栅电极之间。还讨论了相关设备。

20. 发明申请

US20050117383A1 Ferroelectric memory devices having a plate line control circuit and methods for operating the same 失效
公开(公告)号：US20050117383A1
公开(公告)日：2005-06-02
申请号：US11029616
申请日：2005-01-05
申请人： Byung-Gil Jeon , Ki-nam Kim
发明人： Byung-Gil Jeon , Ki-nam Kim
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

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