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    • 14. 发明授权
    • Vertically pinched junction field effect transistor
    • 垂直夹紧结场效应晶体管
    • US08415720B2
    • 2013-04-09
    • US13172036
    • 2011-06-29
    • Badih El-KarehKyu Ok LeeJoo Hyung KimJung Joo Kim
    • Badih El-KarehKyu Ok LeeJoo Hyung KimJung Joo Kim
    • H01L29/66
    • H01L29/66901H01L29/8086
    • A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.
    • CMOS基础技术中的垂直结型场效应晶体管。 垂直结场效应晶体管包括具有源极区和漏极区的半导体衬底,形成在源区和漏区之间的主沟道区,形成在源极区和源极区之间的主沟道区上的阱区, 在源极区域和漏极区域的主沟道区域上分别形成在源极和漏极端部处或仅在阱区域的源极端处的垂直夹断区域,垂直夹点处的源极接触 源极区域中的漏极区域,漏极区域中的垂直夹断区域上的漏极接触,源极接触和漏极接触之间的阱区域上的栅极接触以及在阱区域上形成的浅沟槽隔离。