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    • 12. 发明授权
    • System for context switching between processing elements in a pipeline
of processing elements
    • 用于处理元素流水线中处理元素之间的上下文切换的系统
    • US6101599A
    • 2000-08-08
    • US106244
    • 1998-06-29
    • Michael L. WrightKenneth Michael KeyDarren KerrWilliam E. Jennings
    • Michael L. WrightKenneth Michael KeyDarren KerrWilliam E. Jennings
    • G06F9/30G06F11/08G06F15/16
    • G06F9/461G06F15/17381G06F9/30123H04L49/251H04L49/3063
    • A system and technique facilitate fast context switching among processor complex stages of a pipelined processing engine. Each processor complex comprises a central processing unit (CPU) core having a plurality of internal context switchable registers that are connected to respective registers within CPU cores of the pipelined stages by a processor bus. The technique enables fast context switching by sharing the context switchable registers between upstream and downstream CPUs to, inter alia, force program counters into the downstream registers. In one aspect of the inventive technique, the system automatically reflects (shadows) the contents of an upstream CPU's context switchable registers at respective registers of a downstream CPU over the processor bus. In another aspect of the invention, the system redirects instruction execution by the downstream CPU to an appropriate routine based on processing performed by the upstream CPU.
    • 一种系统和技术有助于在流水线处理引擎的处理器复杂阶段之间进行快速上下文切换。 每个处理器复合体包括具有多个内部上下文可切换寄存器的中央处理单元(CPU)核心,其通过处理器总线连接到流水线级的CPU核心内的相应寄存器。 该技术通过在上游和下游CPU之间共享上下文可切换寄存器来实现快速上下文切换,特别是将程序计数器强制到下游寄存器中。 在本发明技术的一个方面,系统通过处理器总线自动反映(阴影)上游CPU上下文切换寄存器的内容到下游CPU的相应寄存器。 在本发明的另一方面,系统基于上游CPU执行的处理将下游CPU的指令执行重定向到适当的例程。
    • 14. 发明申请
    • Architecture for a processor complex of an arrayed pipelined processing engine
    • 用于处理器阵列的流水线处理引擎的架构
    • US20050125643A1
    • 2005-06-09
    • US11023283
    • 2004-12-27
    • Michael WrightDarren KerrKenneth KeyWilliam Jennings
    • Michael WrightDarren KerrKenneth KeyWilliam Jennings
    • G06F15/78G06F12/00
    • G06F15/8053
    • A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
    • 处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。 处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元(CPU)。 上下文存储器存储瞬时“上下文”数据,以便CPU根据存储在指令存储器中的指令进行处理。 该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路,以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。 该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。
    • 15. 发明申请
    • Method network flow switching and flow data export
    • 方法网络流量切换和流量数据导出
    • US20050027506A1
    • 2005-02-03
    • US10924710
    • 2004-08-23
    • Darren KerrBarry Bruins
    • Darren KerrBarry Bruins
    • H04L12/56G06F9/455
    • H04L45/00H04L45/566H04L47/2441Y10S707/99945Y10S707/99948
    • The invention provides a method and system for switching in networks responsive to message flow patterns. A message “flow” is defined to comprise a set of packets to be transmitted between a particular source and a particular destination. When routers in a network identify a new message flow, they determine the proper processing for packets in that message flow and cache that information for that message flow. Thereafter, when routers in a network identify a packet which is part of that message flow, they process that packet according to the proper processing for packets in that message flow. The proper processing may include a determination of a destination port for routing those packets and a determination of whether access control permits routing those packets to their indicated destination.
    • 本发明提供一种响应消息流模式切换网络的方法和系统。 消息“流”被定义为包括要在特定源和特定目的地之间传送的一组分组。 当网络中的路由器识别新的消息流时,它们确定该消息流中的数据包的适当处理,并缓存该消息流的信息。 此后,当网络中的路由器识别作为该消息流的一部分的分组时,它们根据该消息流中的分组的适当处理来处理该分组。 适当的处理可以包括确定用于路由那些分组的目的地端口以及确定访问控制是否允许将这些分组路由到其指示的目的地。
    • 16. 发明授权
    • Method and apparatus for passing data among processor complex stages of a pipelined processing engine
    • 用于在流水线处理引擎的处理器复杂级之间传递数据的方法和装置
    • US06195739B1
    • 2001-02-27
    • US09106436
    • 1998-06-29
    • Michael L. WrightDarren KerrKenneth Michael KeyWilliam E. Jennings
    • Michael L. WrightDarren KerrKenneth Michael KeyWilliam E. Jennings
    • G06F1500
    • G06F15/8053
    • A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
    • 处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。 处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元(CPU)。 上下文存储器存储瞬时“上下文”数据,以便CPU根据存储在指令存储器中的指令进行处理。 该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路,以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。 该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。
    • 18. 发明授权
    • Architecture for a processor complex of an arrayed pipelined processing engine
    • 用于处理器阵列的流水线处理引擎的架构
    • US06836838B1
    • 2004-12-28
    • US10222277
    • 2002-08-16
    • Michael L. WrightDarren KerrKenneth Michael KeyWilliam E. Jennings
    • Michael L. WrightDarren KerrKenneth Michael KeyWilliam E. Jennings
    • G06F1500
    • G06F15/8053
    • A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
    • 处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。 处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元(CPU)。 上下文存储器存储瞬时“上下文”数据,以便CPU根据存储在指令存储器中的指令进行处理。 该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路,以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。 该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。