专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5374565A Method for ESD protection improvement 失效
标题翻译： ESD保护方法的改进
公开(公告)号：US5374565A
公开(公告)日：1994-12-20
申请号：US139858
申请日：1993-10-22
申请人： Chen-Chiu Hsue , Joe Ko
发明人： Chen-Chiu Hsue , Joe Ko
IPC分类号： H01L27/02 , H01L21/266
CPC分类号： H01L27/0266
摘要： A method of forming an ESD protection device with reduced junction breakdown voltage, simultaneously with an integrated circuit which includes FET devices, and the resultant device structure, are described. A silicon substrate is provided on which there are field oxide regions, gates, and active regions. A first ion implant of a conductivity-imparting dopant is performed in a vertical direction into the active regions of the ESD protection device and the FET devices. A first insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The first insulating layer is patterned to create spacers adjacent to the gates of both the ESD protection device and the FET devices. A second ion implant of a conductivity-imparting dopant with higher concentration than dopant from the first ion implant is performed into active regions of both the ESD protection device and the FET devices. A second insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The second insulating layer is patterned to form contact openings to the active regions. Finally, a third ion implant of a conductivity-imparting dopant, with opposite conductivity from the first and second ion implants, having equal concentration to dopant from the first ion implant, is performed through the contact openings into active regions of the ESD protection device.
摘要翻译：描述了与包括FET器件的集成电路同时形成具有降低的结击穿电压的ESD保护器件的方法以及所得到的器件结构。提供硅基板，其上有场氧化物区域，栅极和有源区域。导电性赋予掺杂剂的第一离子注入在垂直方向上进入ESD保护器件和FET器件的有源区。在ESD保护器件和FET器件上以及场氧化物区域上形成第一绝缘层。图案化第一绝缘层以产生与ESD保护器件和FET器件的栅极相邻的间隔物。与来自第一离子注入的掺杂剂相比，具有更高浓度的导电性赋予掺杂剂的第二离子注入被执行到ESD保护器件和FET器件的有源区。在ESD保护器件和FET器件上以及场氧化物区域上形成第二绝缘层。图案化第二绝缘层以形成到活性区的接触开口。最后，通过所述接触开口将与所述第一和第二离子注入相反的具有与所述第一和第二离子注入物相反的导电性的第三离子注入与所述第一离子注入物的掺杂剂相同地进入到所述ESD保护器件的有源区。

12. 发明授权

US06303455B1 Method for manufacturing capacitor 失效
标题翻译：制造电容器的方法
公开(公告)号：US06303455B1
公开(公告)日：2001-10-16
申请号：US09541450
申请日：2000-03-31
申请人： Chia-Hsin Hou , Tz-Guei Jung , Joe Ko
发明人： Chia-Hsin Hou , Tz-Guei Jung , Joe Ko
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L28/60
摘要： A method for manufacturing a capacitor is provided in the present invention. The bottom electrode of the capacitor is a polysilicon layer, and the top electrode of the capacitor is a silicide layer. Since depletion regions cannot be generated in the metal layer or the suicide layer, and the resistivity of the metal layer or the silicide layer is smaller than a conventional polysilicon layer, so that operating speed and frequency of the capacitor are both increased.
摘要翻译：本发明提供一种电容器的制造方法。电容器的底部电极是多晶硅层，电容器的顶部电极是硅化物层。由于在金属层或硅化物层中不能产生耗尽区，并且金属层或硅化物层的电阻率比常规多晶硅层小，所以电容器的工作速度和频率都增加。

13. 发明授权

US06225219B1 Method of stabilizing anti-reflection coating layer 失效
标题翻译：稳定抗反射涂层的方法
公开(公告)号：US06225219B1
公开(公告)日：2001-05-01
申请号：US09467260
申请日：1999-12-20
申请人： Kan-Yuan Lee , Weiching Horng , Joe Ko , Gary Hong
发明人： Kan-Yuan Lee , Weiching Horng , Joe Ko , Gary Hong
IPC分类号： H01L2144
CPC分类号： H01L21/3105 , G03F7/091 , H01L21/0276 , H01L21/32139 , Y10S438/952
摘要： A method of stabilizing an anti-reflection coating (ARC) layer is disclosed. The method provides a substrate with a dielectric layer, a conductive layer, and the ARC layer formed thereon. The ARC layer is treated in an alloy treatment step prior to forming a photoresist layer over the ARC layer, so that the specificity of the ARC layer is stabilized to allow accurate transfer of a desired pattern. A photomask with the desired pattern is provided, while a photolithographic process is then performed to transfer the pattern onto the wafer.
摘要翻译：公开了一种稳定抗反射涂层（ARC）层的方法。该方法提供了具有介电层，导电层和形成在其上的ARC层的衬底。在ARC层之前形成光致抗蚀剂层之前，在合金处理步骤中处理ARC层，使得ARC层的特异性被稳定以允许精确转移所需图案。提供具有期望图案的光掩模，然后执行光刻工艺以将图案转印到晶片上。

14. 发明授权

US06221761B1 Method of stabilizing anti-reflection coating layer 有权
标题翻译：稳定抗反射涂层的方法
公开(公告)号：US06221761B1
公开(公告)日：2001-04-24
申请号：US09467284
申请日：1999-12-20
申请人： Kan-Yuan Lee , Weiching Horng , Joe Ko , Gary Hong
发明人： Kan-Yuan Lee , Weiching Horng , Joe Ko , Gary Hong
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/3144
摘要： A method of stabilizing an anti-reflection coating (ARC) layer is disclosed. The method provides a substrate with a dielectric layer, a conductive layer, and the ARC layer formed thereon. The ARC layer is treated in an ultraviolet (UV) curing step prior to forming a photoresist layer over the ARC layer, so that the specificity of the ARC layer is stabilized to allow an accurate pattern is replicated in the photoresist layer. A photomask with the desired pattern is provided, while a photolithographic process is then performed to transfer the pattern onto the wafer.
摘要翻译：公开了一种稳定抗反射涂层（ARC）层的方法。该方法提供了具有介电层，导电层和形成在其上的ARC层的衬底。在ARC层之前形成光致抗蚀剂层之前，在紫外（UV）固化步骤中处理ARC层，使得ARC层的特异性被稳定以允许在光致抗蚀剂层中复制精确的图案。提供具有期望图案的光掩模，然后执行光刻工艺以将图案转印到晶片上。

15. 发明授权

US6046938A Structure of a flash memory 有权
标题翻译：闪存结构
公开(公告)号：US6046938A
公开(公告)日：2000-04-04
申请号：US191326
申请日：1998-11-13
申请人： Gary Hong , Wenchi Ting , Joe Ko
发明人： Gary Hong , Wenchi Ting , Joe Ko
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/0416
摘要： A structure of a flash memory is disclosed. The flash memory includes a common drain, a memory unit which has at least one memory cell, and a depletion mode selector transistor. The depletion mode selector transistor isolates the common drain and the memory unit. Two terminals the depletion mode selector transistor are coupled to the common drain and the memory unit, respectively.
摘要翻译：公开了闪速存储器的结构。闪速存储器包括公共漏极，具有至少一个存储单元的存储器单元和耗尽型选择晶体管。耗尽型选择器晶体管将公共漏极和存储器单元隔离。耗尽型选择晶体管的两个端子分别耦合到公共漏极和存储器单元。

16. 发明授权

US5960288A Method of fabricating electrostatic discharge protection device 失效
标题翻译：制造静电放电保护装置的方法
公开(公告)号：US5960288A
公开(公告)日：1999-09-28
申请号：US997874
申请日：1997-12-24
申请人： Gary Hong , Joe Ko
发明人： Gary Hong , Joe Ko
IPC分类号： H01L27/02 , H01L21/265
CPC分类号： H01L27/0266
摘要： A method of fabricating an electrostatic protection device, comprises a semiconductor substrate which includes a first type well, a second type well, and a field oxide layer in between. A first gate, a first spacer, and a first source/drain are formed in the first type well. The second type has a second gate, a second spacer, and the second source/drain formed therein. In addition, an oxide layer is distributed on the first gate, the second gate, a part of the first source/drain, and a part of the second source/drain. A silicide layer is formed on the uncovered first source/drain and the uncovered second source/drain. Therefore, the silicide layer and the gate oxide layer are spaced apart.
摘要翻译：一种制造静电保护装置的方法，包括半导体衬底，其包括第一类型阱，第二类阱和位于其间的场氧化物层。在第一类型的阱中形成第一栅极，第一间隔物和第一源极/漏极。第二类型具有形成在其中的第二栅极，第二间隔物和第二源极/漏极。此外，氧化物层分布在第一栅极，第二栅极，第一源极/漏极的一部分和第二源极/漏极的一部分上。在未覆盖的第一源极/漏极和未覆盖的第二源极/漏极上形成硅化物层。因此，硅化物层和栅极氧化物层间隔开。

17. 发明授权

US5576557A Complementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuits 失效
标题翻译：用于亚微米CMOS集成电路的互补LVTSCR ESD保护电路
公开(公告)号：US5576557A
公开(公告)日：1996-11-19
申请号：US422225
申请日：1995-04-14
申请人： Ming-Dou Ker , Chung-Yu Wu , Hun-Hsien Chang , Chung-Yuan Lee , Joe Ko
发明人： Ming-Dou Ker , Chung-Yu Wu , Hun-Hsien Chang , Chung-Yuan Lee , Joe Ko
IPC分类号： H01L27/02 , H01L29/74
CPC分类号： H01L27/0259 , H01L27/0251
摘要： An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR. The cathode and cathode gate of the second SCR are connected to the second power terminals. The anode of the second SCR is connected to its associated I/O buffering pads. The anode gate of the second SCR is connected to the first power terminal. The ESD circuit also comprises an NMOS transistor having drain, source, gate, and bulk terminals. The NMOS transistor's gate, source and bulk terminals are connected to the second power terminals. The NMOS transistor's drain terminal is connected to the anode gate of the second SCR.
摘要翻译：公开了一种用于保护半导体集成电路（IC）器件的静电放电（ESD）电路。一个ESD电路位于连接到一个引脚和IC的内部电路的每个I / O缓冲焊盘之间。 ESD电路连接到两个电源端子。 ESD电路包括第一和第二低电压触发SCR（LVTSCR），每个具有阳极，阴极，阳极栅极和阴极栅极。第一SCR的阳极和阳极栅极连接到第一电源端子，第一SCR的阴极连接到其I / O缓冲焊盘，第一SCR的阴极栅极连接到第二电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的PMOS晶体管。 PMOS晶体管的栅极，源极和体积端子连接到第一电源端子，PMOS晶体管漏极端子连接到第一SCR的阴极栅极。第二SCR的阴极和阴极栅极连接到第二电源端子。第二SCR的阳极连接到其相关的I / O缓冲垫。第二SCR的阳极栅极连接到第一电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的NMOS晶体管。 NMOS晶体管的栅极，源极和体积端子连接到第二个电源端子。 NMOS晶体管的漏极端子连接到第二SCR的阳极栅极。

18. 发明授权

US5565700A Surface counter doped N-LDD for high carrier reliability 失效
标题翻译：表面积掺杂N-LDD，用于高载流子可靠性
公开(公告)号：US5565700A
公开(公告)日：1996-10-15
申请号：US426491
申请日：1995-04-20
申请人： Jih W. Chou , Joe Ko , Chun Y. Chang
发明人： Jih W. Chou , Joe Ko , Chun Y. Chang
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/7836
摘要： A new surface counter-doped lightly doped source and drain integrated circuit field effect transistor device is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions. A thin layer of silicon oxide is deposited over the surface of the polysilicon gate electrode structure and is anisotropically etched to form ultra thin spacers on the sidewalls of the polysilicon gate electrode structure. A third ion implantation is performed with no tilt angle to complete formation of the lightly doped drain regions. A glasseous layer is deposited over all surfaces of the substrate and flowed followed by metallization and passivation to complete manufacture of the integrated circuit.
摘要翻译：描述了新的表面反掺杂轻掺杂源极和漏极集成电路场效应晶体管器件。在硅衬底上形成栅氧化硅层。一层多晶硅沉积在栅极氧化硅层上并被蚀刻以形成栅电极结构。以倾斜角度执行第一离子注入，以在半导体衬底中形成轻掺杂漏极区域，其中轻掺杂漏极区域被栅电极结构部分地重叠。以比第一离子注入更大的倾斜角度和更低的能量执行第二离子注入，其中第二离子注入反掺杂轻掺杂的漏极区的表面以形成非常轻掺杂的漏极层，从而使轻掺杂漏极区埋葬地区。氧化硅薄层沉积在多晶硅栅电极结构的表面上，并被各向异性蚀刻以在多晶硅栅电极结构的侧壁上形成超薄间隔物。执行没有倾斜角的第三离子注入以完成轻掺杂漏极区的形成。在基板的所有表面上沉积一层胶层，然后流动，随后进行金属化和钝化以完成集成电路的制造。

19. 发明授权

US5434108A Grounding method to eliminate the antenna effect in VLSI process 失效
标题翻译：在VLSI过程中消除天线效应的接地方法
公开(公告)号：US5434108A
公开(公告)日：1995-07-18
申请号：US124647
申请日：1993-09-22
申请人： Joe Ko , Chen-Chiu Hsue
发明人： Joe Ko , Chen-Chiu Hsue
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/465
CPC分类号： H01L21/28123 , H01L21/32136 , H01L21/32137
摘要： A method of subjecting an integrated circuit, having electrically grounded elements and large first metal regions on its surface which are connected to device structures, to a plasma process, is described. Large first metal regions are connected to the electrically grounded elements. The integrated circuit is placed in a chamber for accomplishing the plasma process. The integrated circuit is subjected to the plasma process such that the connecting of the large first metal regions to the electrically grounded elements prevents damage to the device structures. The integrated circuit is removed from the chamber. Finally, the large first metal regions are disconnected from the electrically grounded elements.
摘要翻译：描述了将具有电接地元件的集成电路及其与器件结构连接的表面上的大的第一金属区域进行等离子体处理的方法。大的第一金属区域连接到电接地元件。将集成电路放置在用于完成等离子体处理的室中。对集成电路进行等离子体处理，使得大的第一金属区域与电接地元件的连接防止对器件结构的损坏。集成电路从腔室中取出。最后，大的第一金属区域与电接地元件断开。

20. 发明授权

US06309925B1 Method for manufacturing capacitor 失效
标题翻译：制造电容器的方法
公开(公告)号：US06309925B1
公开(公告)日：2001-10-30
申请号：US09643211
申请日：2000-08-22
申请人： Tz-Guei Jung , Chia-Hsin Hou , Joe Ko
发明人： Tz-Guei Jung , Chia-Hsin Hou , Joe Ko
IPC分类号： H01L218242
CPC分类号： H01L27/0629 , H01L28/40
摘要： A method for manufacturing a capacitor. A semiconductor substrate is divided into a peripheral circuit region and a memory cell region. An isolation structure is formed in the memory cell region. A gate oxide layer is formed over the substrate outside the isolation structure. A polysilicon layer is formed over the gate oxide layer and the isolation structure. The polysilicon layer and the gate oxide layer are patterned to form a bottom electrode above the isolation structure. In the meantime a polysilicon gate electrode is also formed above the peripheral circuit region. Spacers are formed on the sidewalls of the polysilicon gate electrode and the bottom electrode. A metal silicide layer is formed over the bottom electrode and the polysilicon gate electrode. A dielectric layer is formed over the metal silicide layer above the bottom electrode. A metallic layer is formed over the dielectric layer to form a capacitor.
摘要翻译：一种制造电容器的方法。半导体衬底被分成外围电路区域和存储单元区域。在存储单元区域中形成隔离结构。在隔离结构外部的衬底上形成栅氧化层。在栅极氧化物层和隔离结构上形成多晶硅层。图案化多晶硅层和栅极氧化物层以在隔离结构上方形成底部电极。同时，在外围电路区域上方也形成多晶硅栅电极。隔板形成在多晶硅栅电极和底电极的侧壁上。在底部电极和多晶硅栅电极上形成金属硅化物层。在底部电极上方的金属硅化物层上形成介电层。在电介质层上形成金属层以形成电容器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式