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11. 发明授权

US06232160B1 Method of delta-channel in deep sub-micron process 有权
标题翻译：深亚微米工艺中δ沟道的方法
公开(公告)号：US06232160B1
公开(公告)日：2001-05-15
申请号：US09396515
申请日：1999-09-15
申请人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee
发明人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee
IPC分类号： H01L21336
CPC分类号： H01L29/66537 , H01L29/1045 , H01L29/66553 , H01L29/6659
摘要： A new method of suppressing short channel effect without increasing junction leakage and capacitance using a single self-aligning delta-channel implant is described. A pad oxide layer is formed over a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer and patterned to leave an opening where a gate electrode will be formed. Dielectric spacers are formed on the sidewalls of the opening wherein a portion of the substrate is not covered by the spacers within the opening. A single delta-channel implant is made into the semiconductor substrate using the silicon nitride layer and the dielectric spacers as a mask. This delta-channel implant suppresses short channel effect without increasing junction leakage and capacitance. The dielectric spacers are removed. A polysilicon layer is deposited over the silicon nitride layer and within the opening and polished to leave the polysilicon layer only within the opening. The silicon nitride layer is removed to form a gate electrode wherein the delta-channel implant underlies the gate electrode. Thereafter, lightly doped regions and source and drain regions are formed within the semiconductor substrate associated with the gate electrode to complete fabrication of the integrated circuit device.
摘要翻译：描述了使用单个自对准delta通道植入物抑制短通道效应而不增加结漏电和电容的新方法。衬垫氧化物层形成在半导体衬底上。将氮化硅层沉积在衬垫氧化物层上并被图案化以留下将形成栅电极的开口。电介质间隔物形成在开口的侧壁上，其中衬底的一部分未被开口内的间隔物覆盖。使用氮化硅层和电介质间隔物作为掩模将单个Δ沟道注入制成半导体衬底。该delta通道注入抑制短沟道效应，而不增加结漏电流。去除电介质垫片。多晶硅层沉积在氮化硅层之上并且在开口内被抛光，仅在开口内离开多晶硅层。去除氮化硅层以形成栅电极，其中该三角沟道注入位于该栅电极下方。此后，在与栅极电极相关联的半导体衬底内形成轻掺杂区域和源极和漏极区域，以完成集成电路器件的制造。

12. 发明授权

US06207482B1 Integration method for deep sub-micron dual gate transistor design 有权
标题翻译：深亚微米双栅晶体管设计的集成方法
公开(公告)号：US06207482B1
公开(公告)日：2001-03-27
申请号：US09346528
申请日：1999-07-02
申请人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee , Chia-Hung Tunga
发明人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee , Chia-Hung Tunga
IPC分类号： H01L218238
CPC分类号： H01L29/66537 , H01L21/26586 , H01L21/823807 , H01L21/823842
摘要： The invention provides a gate pocket implantation and post-processing sequence that allows for the creation of a deep and narrow pocket implant without affecting gate threshold voltage and the integrity of the gate oxide layer.
摘要翻译：本发明提供了一种门口注入和后处理顺序，其允许创建深而窄的口袋注入而不影响栅极阈值电压和栅极氧化物层的完整性。

13. 发明授权

US07247543B2 Decoupling capacitor 有权
标题翻译：去耦电容
公开(公告)号：US07247543B2
公开(公告)日：2007-07-24
申请号：US11072014
申请日：2005-03-04
申请人： Jiaw-Ren Shih , Jian-Hsing Lee , Shui-Hung Chen
发明人： Jiaw-Ren Shih , Jian-Hsing Lee , Shui-Hung Chen
IPC分类号： H01L23/62
CPC分类号： H01L27/0251
摘要： A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.
摘要翻译：在集成电路（IC）上提供了具有增加的静电放电阻抗（ESD）的去耦电容器。电容器可以是单指或多指。在一个示例中，电容器包括由电介质材料隔开的第一和第二电极，靠近第一电极定位的源，以及靠近第一电极定位并与第一电极分离的浮动漏极。通过源极，浮置漏极和掺杂区域之间的电流相互作用形成了被建模为双极结型晶体管（BJT）的寄生元件。浮动漏极在BJT的基极处提供恒定的电位区域，从而最大程度降低对IC的ESD损坏。

14. 发明授权

US06937457B2 Decoupling capacitor 有权
标题翻译：去耦电容
公开(公告)号：US06937457B2
公开(公告)日：2005-08-30
申请号：US10694129
申请日：2003-10-27
申请人： Jiaw-Ren Shih , Jian-Hsing Lee , Shui-Hung Chen
发明人： Jiaw-Ren Shih , Jian-Hsing Lee , Shui-Hung Chen
IPC分类号： H01G4/228 , H01G4/35 , H01L21/8234 , H01L23/60 , H02H9/00
CPC分类号： H01L27/0251
摘要： A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.
摘要翻译：在集成电路（IC）上提供了具有增加的静电放电阻抗（ESD）的去耦电容器。电容器可以是单指或多指。在一个示例中，电容器包括由电介质材料隔开的第一和第二电极，靠近第一电极定位的源，以及靠近第一电极定位并与第一电极分离的浮动漏极。通过源极，浮置漏极和掺杂区域之间的电流相互作用形成了被建模为双极结型晶体管（BJT）的寄生元件。浮动漏极在BJT的基极处提供恒定的电位区域，从而最大程度降低对IC的ESD损坏。

15. 发明授权

US06888248B2 Extended length metal line for improved ESD performance 失效
标题翻译：延长金属线，提高ESD性能
公开(公告)号：US06888248B2
公开(公告)日：2005-05-03
申请号：US10401090
申请日：2003-03-26
申请人： Shui-Hung Chen , Jian-Hsing Lee , Jiaw-Ren Shih
发明人： Shui-Hung Chen , Jian-Hsing Lee , Jiaw-Ren Shih
IPC分类号： H01L23/60 , H01L27/02 , H01L23/48
CPC分类号： H01L27/0288 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.
摘要翻译：公开了一种多级金属互连结构及其形成方法，用于改善CMOS晶体管对静电放电（ESD）瞬变事件的电阻。一种半导体器件，包括至少一个NMOS晶体管，沿着至少一个电路通路电连接到输入/输出信号源和参考电压电位; 并且至少通过将金属互连线长度部分的至少一部分压缩成在所述金属互连线长度部分的预定体积内的蛇形形状，将至少一个所述输入/输出信号源电连接至所述至少一个NMOS晶体管，半导体器件。

16. 发明申请

US20050088801A1 DECOUPLING CAPACITOR 有权
标题翻译：解除电容器
公开(公告)号：US20050088801A1
公开(公告)日：2005-04-28
申请号：US10694129
申请日：2003-10-27
申请人： Jiaw-Ren Shih , Jian-Hsing Lee , Shui-Hung Chen
发明人： Jiaw-Ren Shih , Jian-Hsing Lee , Shui-Hung Chen
IPC分类号： H01G4/228 , H01G4/35 , H01L21/8234 , H01L23/60 , H02H9/00
CPC分类号： H01L27/0251
摘要： A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.
摘要翻译：在集成电路（IC）上提供了具有增加的静电放电阻抗（ESD）的去耦电容器。电容器可以是单指或多指。在一个示例中，电容器包括由电介质材料隔开的第一和第二电极，靠近第一电极定位的源，以及靠近第一电极定位并与第一电极分离的浮动漏极。通过源极，浮置漏极和掺杂区域之间的电流相互作用形成了被建模为双极结型晶体管（BJT）的寄生元件。浮动漏极在BJT的基极处提供恒定的电位区域，从而最大程度降低对IC的ESD损坏。

17. 发明授权

US06762439B1 Diode for power protection 有权
标题翻译：二极管用于电源保护
公开(公告)号：US06762439B1
公开(公告)日：2004-07-13
申请号：US09898386
申请日：2001-07-05
申请人： Shui-Hung Chen , Jian-Hsing Lee , Jiaw-Ren Shih , Ta-Lee Yu
发明人： Shui-Hung Chen , Jian-Hsing Lee , Jiaw-Ren Shih , Ta-Lee Yu
IPC分类号： H01L2974
CPC分类号： H01L27/0262 , H01L29/7436
摘要： A new electrostatic discharge protection device is achieved. A p-well region is in a semiconductor substrate. An n+ region in the p-well region is connected to a first voltage supply. An n-well region in the p-well region is spaced from the n+ region such that a depletion region will extend therebetween during normal operation. A p+ region in the n-well region is connected to a second voltage supply of greater value than the first voltage supply during normal operation. Current is conducted through the n+ region to the p+ region during an electrostatic discharge event.
摘要翻译：实现了新的静电放电保护装置。 p阱区位于半导体衬底中。 p阱区域中的n +区域连接到第一电压源。 p阱区域中的n阱区域与n +区域间隔开，使得在正常操作期间耗尽区域将在其间延伸。在正常操作期间，n阱区域中的p +区域连接到比第一电压源更大的值的第二电压源。在静电放电事件期间，电流通过n +区域传导到p +区域。

18. 发明授权

US06214670B1 Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance 有权
标题翻译：制造具有出色的热载体性能的短沟道金属栅CMOS器件的方法
公开(公告)号：US06214670B1
公开(公告)日：2001-04-10
申请号：US09358986
申请日：1999-07-22
申请人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee
发明人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee
IPC分类号： H01L21336
CPC分类号： H01L29/66613 , H01L29/7834
摘要： In short-channel MOSFET devices with gates constructed using conventional double-diffusing techniques, damage to the silicon substrate region near the gate structure causes hot carrier effects that degrade the device performance. The inventive process described minimizes damage to the silicon substrate in the region of the metal gate structure thereby providing a MOSFET device with superior hot carrier effect performance.
摘要翻译：在采用常规双重扩散技术构造的栅极的短沟道MOSFET器件中，栅极结构附近的硅衬底区域的损坏会导致热载流子效应降低器件性能。所描述的本发明方法使得在金属栅极结构的区域中对硅衬底的损坏最小化，从而提供具有优异热载流子效应性能的MOSFET器件。

19. 发明授权

US06645820B1 Polycrystalline silicon diode string for ESD protection of different power supply connections 有权
标题翻译：多晶硅二极管串用于ESD保护的不同电源连接
公开(公告)号：US06645820B1
公开(公告)日：2003-11-11
申请号：US10119337
申请日：2002-04-09
申请人： Kuo Reay Peng , Jian-Hsing Lee , Shui-Hung Chen
发明人： Kuo Reay Peng , Jian-Hsing Lee , Shui-Hung Chen
IPC分类号： H01L21331
CPC分类号： H01L29/861 , H01L27/0255 , Y10S438/979 , Y10S438/983
摘要： An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit has a string of serially connected lateral polycrystalline silicon diodes characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.
摘要翻译：当ESD事件在多个单独的电源电压源之间引起过大的差分电压时，ESD保护电路保护具有多个电源电压源的集成电路免受损坏。 ESD保护电路具有一串串联连接的横向多晶硅二极管，其特征在于一致的开启阈值电压电平，使得随着ESD保护电路的级数增加，ESD保护电路的导通电压阈值线性增加。

20. 发明授权

US06876041B2 ESD protection component 有权
标题翻译： ESD保护元件
公开(公告)号：US06876041B2
公开(公告)日：2005-04-05
申请号：US09974056
申请日：2001-10-11
申请人： Jian-Hsing Lee , Kuo-Reay Peng , Shui-Hung Chen
发明人： Jian-Hsing Lee , Kuo-Reay Peng , Shui-Hung Chen
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0266 , H01L29/87 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an ESD protection component, comprising at least two MOS field effect transistors (FETs) of a first conductivity type and a first well having a first conductivity type. The two MOS FETs have two parallel gates formed on a first semiconductive layer having a second conductivity type. The first well formed on the first semiconductive layer is comprised of a connecting area formed between the MOS FETs, two parallel extension areas formed perpendicular to the gates of the MOS FETs, and a first doping area of the second conductivity type formed in the connecting area. Two SCR are formed with drains of the MOS FETs, the first semiconductive layer, the first well and the first doping region. With the combination of the SCR and NMOS FET, ESD protection efficiency can be substantially enhanced.
摘要翻译：本发明提供一种ESD保护元件，包括至少两个具有第一导电类型的MOS场效应晶体管（FET）和具有第一导电类型的第一阱。两个MOS FET具有形成在具有第二导电类型的第一半导体层上的两个平行栅极。形成在第一半导体层上的第一阱包括形成在MOS FET之间的连接区域，垂直于MOS FET的栅极形成的两个平行延伸区域和形成在连接区域中的第二导电类型的第一掺杂区域。两个SCR形成有MOS FET的漏极，第一半导体层，第一阱和第一掺杂区。通过SCR和NMOS FET的组合，可以显着提高ESD保护效率。

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