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11. 发明授权

US08717391B2 User interface pipe scalers with active regions 有权
标题翻译：用户界面管道缩放器与活动区域
公开(公告)号：US08717391B2
公开(公告)日：2014-05-06
申请号：US12950267
申请日：2010-11-19
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
IPC分类号： G09G5/00 , G06F13/00 , G09G5/02
CPC分类号： G09G5/024 , G09G5/022 , G09G5/14 , G09G5/363 , G09G5/397
摘要： A display pipe may include fetch circuitry and a scaler unit, and registers programmable with information that defines active regions of an image frame. Pixels within the active regions are active pixels to be displayed, pixels outside of the active regions are inactive pixels not to be displayed. The fetch circuitry may retrieve frames from memory, retrieving the active pixels and not retrieving the inactive pixels as defined by the programmed contents of the registers. A scaler unit may produce scaled pixels from the fetched pixels, basing each scaled pixel on a respective corresponding set of pixels. When a given pixel of the respective corresponding set of pixels is an inactive pixel, the scaler unit may assign an estimated value to the given pixel based on one or more active pixels in the respective corresponding set of pixels. The scaler unit may provide the scaled pixels to a blend unit for blending with other pixels.
摘要翻译：显示管可以包括提取电路和缩放器单元，并且可以用定义图像帧的有效区域的信息来编程。活动区域内的像素是要显示的活动像素，活动区域之外的像素是不显示的不活动像素。提取电路可以从存储器检索帧，检索有效像素，而不检索由寄存器的编程内容定义的非活动像素。缩放器单元可以从获取的像素产生缩放的像素，将每个缩放的像素基于相应的相应的像素集。当相应的相应像素集合的给定像素是非活动像素时，缩放器单元可以基于相应的相应像素集合中的一个或多个有效像素来分配给定像素的估计值。缩放器单元可以将缩放的像素提供给用于与其他像素混合的混合单元。

12. 发明申请

US20130322746A1 SYSTEMS AND METHODS FOR YCC IMAGE PROCESSING 有权
标题翻译： YCC图像处理系统与方法
公开(公告)号：US20130322746A1
公开(公告)日：2013-12-05
申请号：US13484926
申请日：2012-05-31
申请人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Simon Wolfenden Butler , Mark A. Zimmer , Joseph P. Bratt
发明人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Simon Wolfenden Butler , Mark A. Zimmer , Joseph P. Bratt
IPC分类号： G06K9/40
CPC分类号： G06T1/20 , G06T3/4015
摘要： Systems and methods for processing YCC image data provided. In one example, an electronic device includes memory to store image data in RGB or YCC format and a YCC image processing pipeline to process the image data. The YCC image processing pipeline may include receiving logic configured to receive the image data in RGB or YCC format and color space conversion logic configured to, when the image data is received in RGB format, convert the image data into YCC format. The YCC image processing logic may also include luma sharpening and chroma suppression logic; brightness, contrast, and color adjustment logic; gamma logic; chroma decimation logic; scaling logic; and chromanoise reduction logic.
摘要翻译：用于处理提供的YCC图像数据的系统和方法。在一个示例中，电子设备包括以RGB或YCC格式存储图像数据的存储器和用于处理图像数据的YCC图像处理流水线。 YCC图像处理流水线可以包括被配置为接收RGB或YCC格式的图像数据的接收逻辑，以及配置为当以RGB格式接收图像数据时将图像数据转换为YCC格式的颜色空间转换逻辑。 YCC图像处理逻辑还可以包括亮度锐化和色度抑制逻辑; 亮度，对比度和颜色调整逻辑; 伽玛逻辑; 色度抽取逻辑; 缩放逻辑; 和色度降低逻辑。

13. 发明申请

US20130322745A1 Local Image Statistics Collection 有权
标题翻译：本地图像统计信息收集
公开(公告)号：US20130322745A1
公开(公告)日：2013-12-05
申请号：US13484741
申请日：2012-05-31
申请人： Suk Hwan Lim , D. Amnon Silverstein , Guy Cote , Steven David Hordley , Graham Finlayson , Weichun Ku , Joseph P. Bratt
发明人： Suk Hwan Lim , D. Amnon Silverstein , Guy Cote , Steven David Hordley , Graham Finlayson , Weichun Ku , Joseph P. Bratt
IPC分类号： G06K9/36
CPC分类号： H04N9/73 , H04N5/142 , H04N9/045 , H04N9/735 , H04N2209/046
摘要： Systems and methods for generating local image statistics are provided. In one example, an image signal processing system may include a statistics pipeline with image processing logic and local image statistics collection logic. The image processing logic may receive and process pixels of raw image data. The local image statistics collection logic may generate a local histogram associated with a luminance of the pixels of a first block of pixels of the raw image data or a thumbnail in which a pixel of the thumbnail represents a downscaled version of the luminance of the pixels of the first block of the pixel. The raw image data may include many other blocks of pixels of the same size as the first block of pixels.
摘要翻译：提供了生成本地图像统计信息的系统和方法。在一个示例中，图像信号处理系统可以包括具有图像处理逻辑和本地图像统计信息收集逻辑的统计流水线。图像处理逻辑可以接收和处理原始图像数据的像素。本地图像统计收集逻辑可以生成与原始图像数据的第一像素块的像素的亮度相关联的局部直方图或缩略图，其中缩略图的像素表示缩略图的像素的亮度像素的第一个块。原始图像数据可以包括与第一像素块相同尺寸的许多其他像素块。

14. 发明授权

US08508612B2 Image signal processor line buffer configuration for processing ram image data 有权
标题翻译：用于处理原始图像数据的图像信号处理器线缓冲器配置
公开(公告)号：US08508612B2
公开(公告)日：2013-08-13
申请号：US12895396
申请日：2010-09-30
申请人： Guy Côté , Jeffrey E. Frederiksen , Joseph P. Bratt
发明人： Guy Côté , Jeffrey E. Frederiksen , Joseph P. Bratt
IPC分类号： H04N5/228
CPC分类号： H04N9/045 , G06T3/4015
摘要： The present disclosure provides techniques relates to the implementation of a raw pixel processing unit using a set of line buffers. In one embodiment, the set of line buffers may include a first subset and second subset. Various logical units of the raw pixel processing unit may be implemented using the first and second subsets of line buffers in a shared manner. For instance, in one embodiment, defective pixel correction and detection logic may be implemented using the first subset of line buffers. The second subset of line buffers may be used to implement lens shading correction logic, gain, offset, and clamping logic, and demosaicing logic. Further, noise reduction may also be implemented using at least a portion of each of the first and second subsets of line buffers.
摘要翻译：本公开提供了技术涉及使用一组行缓冲器的原始像素处理单元的实现。在一个实施例中，行缓冲器组可以包括第一子集和第二子集。可以以共享的方式使用第一和第二子行的行缓冲器来实现原始像素处理单元的各种逻辑单元。例如，在一个实施例中，可以使用线缓冲器的第一子集来实现有缺陷的像素校正和检测逻辑。行缓冲器的第二子集可用于实现镜头阴影校正逻辑，增益，偏移和钳位逻辑以及去马赛克逻辑。此外，还可以使用行缓冲器的第一和第二子集中的每一个的至少一部分来实现噪声降低。

15. 发明申请

US20120151104A1 PIO INTERJECTION BETWEEN BEATS OF A DMA OPERATION 有权
标题翻译： DMA操作之间的PIO间隔
公开(公告)号：US20120151104A1
公开(公告)日：2012-06-14
申请号：US12966946
申请日：2010-12-13
申请人： Joseph P. Bratt , Lakshmi Rao
发明人： Joseph P. Bratt , Lakshmi Rao
IPC分类号： G06F13/36 , G06F13/28
CPC分类号： G06F13/28
摘要： Techniques are disclosed relating to detecting and interjecting a programmed input/output (PIO) operation into a direct memory access (DMA) operation. In one embodiment, an integrated circuit may include a DMA controller that may contain a control circuit, a DMA unit, and a PIO unit. The control circuit may be configured to detect a pending PIO operation during a DMA operation and interject the PIO operation onto a shared path during the same clock cycle as or the first clock cycle following the detection of the pending PIO operation. The DMA operation may consist of multiple single-clock-cycle beats. In one embodiment, a PIO operation may be interjected onto the shared path between beats of a DMA operation, on consecutive clock cycles. At the next clock cycle following the PIO operation, the control circuit may resume the next beat of the DMA operation.
摘要翻译：公开了关于将编程的输入/输出（PIO）操作检测和插入到直接存储器访问（DMA）操作中的技术。在一个实施例中，集成电路可以包括可以包含控制电路，DMA单元和PIO单元的DMA控制器。控制电路可以被配置为在DMA操作期间检测待处理的PIO操作，并且在与待处理的PIO操作的检测之后的相同时钟周期期间或在第一时钟周期之后将PIO操作插入到共享路径上。 DMA操作可以由多个单时钟周期节拍组成。在一个实施例中，可以在连续的时钟周期上将PIO操作插入在DMA操作的节拍之间的共享路径上。在PIO操作之后的下一个时钟周期，控制电路可以恢复DMA操作的下一个节拍。

16. 发明申请

US20120127193A1 User Interface Pipe Scalers with Active Regions 有权
标题翻译：用户界面活动区域的管道定标器
公开(公告)号：US20120127193A1
公开(公告)日：2012-05-24
申请号：US12950267
申请日：2010-11-19
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
IPC分类号： G09G5/02 , G09G5/00
CPC分类号： G09G5/024 , G09G5/022 , G09G5/14 , G09G5/363 , G09G5/397
摘要： A display pipe may include fetch circuitry and a scaler unit, and registers programmable with information that defines active regions of an image frame. Pixels within the active regions are active pixels to be displayed, pixels outside of the active regions are inactive pixels not to be displayed. The fetch circuitry may retrieve frames from memory, retrieving the active pixels and not retrieving the inactive pixels as defined by the programmed contents of the registers. A scaler unit may produce scaled pixels from the fetched pixels, basing each scaled pixel on a respective corresponding set of pixels. When a given pixel of the respective corresponding set of pixels is an inactive pixel, the scaler unit may assign an estimated value to the given pixel based on one or more active pixels in the respective corresponding set of pixels. The scaler unit may provide the scaled pixels to a blend unit for blending with other pixels.
摘要翻译：显示管可以包括提取电路和缩放器单元，并且可以用定义图像帧的有效区域的信息来编程。活动区域内的像素是要显示的活动像素，活动区域之外的像素是不显示的不活动像素。提取电路可以从存储器检索帧，检索有效像素，而不检索由寄存器的编程内容定义的非活动像素。缩放器单元可以从获取的像素产生缩放的像素，将每个缩放的像素基于相应的相应的像素集。当相应的相应像素集合的给定像素是非活动像素时，缩放器单元可以基于相应的相应像素集合中的一个或多个有效像素来分配给定像素的估计值。缩放器单元可以将缩放的像素提供给用于与其他像素混合的混合单元。

17. 发明申请

US20120127187A1 Error Check-Only Mode 有权
标题翻译：错误检查模式
公开(公告)号：US20120127187A1
公开(公告)日：2012-05-24
申请号：US12950239
申请日：2010-11-19
申请人： Joseph P. Bratt , Peter F. Holland , David L. Bowman
发明人： Joseph P. Bratt , Peter F. Holland , David L. Bowman
IPC分类号： G09G5/36
CPC分类号： G09G5/397 , G09G5/36 , G09G2330/12 , G09G2340/0407 , G09G2340/06 , G09G2340/10 , G09G2340/125 , G09G2360/10 , G09G2360/125
摘要： Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available. The results generated by the error-checking may be read and compared to an expected value to detect test pass/fail conditions.
摘要翻译：视频显示管道可以用FIFO（先进先出）缓冲器终止，从而将像素提供给显示控制器以在图形/视频显示器上显示像素。显示管道可以以比显示控制器从FIFO缓冲器提取像素的速率高得多的速率来频繁地处理像素。在仅错误检查模式中，FIFO可以被禁用，并且连接在FIFO前面的错误校验（例如CRC）块可以像显示管能够处理显示管一样快地接收由显示管处理的像素像素。因此，执行测试所需的测试/模拟时间的长度可以由生成像素的速率而不是显示控制器显示像素的速率来确定。在不支持显示或不可用的环境中也可以进行测试/模拟。可以读取错误检查产生的结果并将其与期望值进行比较，以检测测试通过/失败条件。

18. 发明申请

US20120081577A1 IMAGE SENSOR DATA FORMATS AND MEMORY ADDRESSING TECHNIQUES FOR IMAGE SIGNAL PROCESSING 有权
标题翻译：用于图像信号处理的图像传感器数据格式和存储器寻址技术
公开(公告)号：US20120081577A1
公开(公告)日：2012-04-05
申请号：US12895346
申请日：2010-09-30
申请人： Guy Côté , Jeffrey E. Frederiksen , Joseph P. Bratt , Jung Wook Cho
发明人： Guy Côté , Jeffrey E. Frederiksen , Joseph P. Bratt , Jung Wook Cho
IPC分类号： H04N5/76
CPC分类号： H04N5/772 , H04N5/23229 , H04N5/23235 , H04N5/2354 , H04N5/3572 , H04N5/367 , H04N9/045 , H04N9/735 , H04N19/80
摘要： Certain embodiments of the present disclosure provide a flexible memory input/output controller that is configured to the storing and reading of multiple types of pixels and pixel memory formats. For instance, the memory I/O controller may support the storing and reading of raw image pixels at various bits of precision, such as 8-bit, 10-bit, 12-bit, 14-bit, and 16-bit. Pixel formats that are unaligned with memory bytes (e.g., not being a multiple of 8-bits) may be stored in a packed manner. The memory I/O controller may also support various formats of RGB pixel sets and YCC pixel sets.
摘要翻译：本公开的某些实施例提供了一种灵活的存储器输入/输出控制器，其被配置为存储和读取多种类型的像素和像素存储器格式。例如，存储器I / O控制器可以支持以各种精度位（例如8位，10位，12位，14位和16位）存储和读取原始图像像素。与存储器字节不对齐的像素格式（例如，不是8位的倍数）可以以打包的方式存储。存储器I / O控制器还可以支持RGB像素集和YCC像素集的各种格式。

19. 发明授权

US5572704A System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes 失效
标题翻译：用于控制多处理器系统中的分级缓存的系统和方法，包括数据丢失和死锁预防方案
公开(公告)号：US5572704A
公开(公告)日：1996-11-05
申请号：US167005
申请日：1993-12-15
申请人： Joseph P. Bratt , John Brennan , Peter Y. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavagia
发明人： Joseph P. Bratt , John Brennan , Peter Y. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavagia
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0811
摘要： A method for preventing data loss and deadlock in a multi-processor computer system wherein at least one processor in the computer system includes a split-level cache. The split-level cache has a byte-writable first-level and a word-writable second level. The method monitors the second level cache to determine if a forced atomic (FA) instruction is in a second level cache pipeline. If an FA instruction is determined to be in the second level cache pipeline, then interventions to the second level cache are delayed until the FA instruction exits the second level cache pipeline. In this manner data written by operation of cache memory access instruction that cause the interventions is not destroyed by the execution of the FA instruction, thereby preventing data loss. The method also monitors the second level cache pipeline to determine if a possible miss (PM) instruction is in the second level cache pipeline. If a PM instruction is determined to be in the second level cache pipeline, the FA instructions are prevented from entering the second level cache pipeline such that execution of interventions to the second level cache is not prevented when an instruction in the second level cache may be detained to process an intervention in its behalf, thereby preventing deadlock between processing units of the computer system.
摘要翻译：一种用于在多处理器计算机系统中防止数据丢失和死锁的方法，其中所述计算机系统中的至少一个处理器包括分级高速缓存。分级缓存具有可写字节的第一级和可写字的第二级。该方法监视第二级高速缓存以确定强制原子（FA）指令是否在二级高速缓存流水线中。如果FA指令被确定在第二级高速缓存流水线中，则延迟到第二级高速缓存的干预，直到FA指令退出第二级高速缓存流水线。以这种方式，通过执行FA指令不会破坏导致干预的高速缓冲存储器访问指令的操作所写入的数据，从而防止数据丢失。该方法还监视第二级高速缓存流水线以确定可能的未命中（PM）指令是否在第二级高速缓存流水线中。如果确定PM指令处于第二级高速缓存流水线中，则FA指令被阻止进入第二级高速缓存流水线，使得当第二级高速缓存中的指令可能为被拘留以代表其进行干预，从而防止计算机系统的处理单元之间的僵局。

20. 发明授权

US08749568B2 Parameter FIFO 有权
公开(公告)号：US08749568B2
公开(公告)日：2014-06-10
申请号：US12685166
申请日：2010-01-11
申请人： Joseph P. Bratt , Shing Choo , Peter F. Holland , Timothy J. Millet
发明人： Joseph P. Bratt , Shing Choo , Peter F. Holland , Timothy J. Millet
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G09G5/14 , G09G5/363 , G09G2340/10 , G09G2360/12 , G09G2360/127
摘要： A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

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