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    • 11. 发明申请
    • DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
    • 用于增加铜互连结构中电磁寿命的电介质障碍层
    • US20070190784A1
    • 2007-08-16
    • US11736402
    • 2007-04-17
    • Hao CuiPeter BurkeWilbur Catabay
    • Hao CuiPeter BurkeWilbur Catabay
    • H01L21/44
    • H01L21/76832H01L21/76825H01L21/76826H01L21/76834H01L21/76883
    • Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.
    • 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分,第一部分具有相对于第二部分具有改进的铜的粘合性,并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着,以增加堆叠中这种材料的浓度。
    • 12. 发明授权
    • Planarization with reduced dishing
    • 平面化减少凹陷
    • US07220362B2
    • 2007-05-22
    • US11337460
    • 2006-01-23
    • Wilbur G. CatabayWei-Jen HsiaHao Cui
    • Wilbur G. CatabayWei-Jen HsiaHao Cui
    • B44C1/22H01L21/302
    • B23H5/08C23F1/02C23F4/00C25F3/02H01L21/02063H01L21/32115H01L21/3212H01L21/32136H01L21/7684
    • A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.
    • 在衬底上形成平坦化层的方法,其中衬底被清洁,并且形成具有高部分和低部分的表面的层。 电阻掩模形成在层的低部分上,但不在层的高部分之上。 蚀刻层的表面,其中层的高部分暴露于蚀刻,但是电阻掩模下面的层的低部分不暴露于蚀刻。 层的表面的蚀刻继续进行直到层的高部分与层的低部分基本相同的水平,从而提供层的表面的初始平坦化。 电阻掩模从层的表面去除,并且层的所有表面被平坦化以提供平坦化层。
    • 16. 发明授权
    • Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
    • 用于增加铜互连结构中的电迁移寿命的介电阻挡层
    • US08043968B2
    • 2011-10-25
    • US12764004
    • 2010-04-20
    • Hao CuiPeter A. BurkeWilbur G. Catabay
    • Hao CuiPeter A. BurkeWilbur G. Catabay
    • H01L21/00
    • H01L21/76832H01L21/76825H01L21/76826H01L21/76834H01L21/76883
    • Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.
    • 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分,第一部分具有相对于第二部分提高的对铜的粘附性,并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着,以增加堆叠中这种材料的浓度。