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11. 发明申请

US20130346935A1 SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION 有权
公开(公告)号：US20130346935A1
公开(公告)日：2013-12-26
申请号：US14012142
申请日：2013-08-28
申请人： Young-Chow PENG , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
发明人： Young-Chow PENG , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.

12. 发明授权

US07973552B2 On-die terminators formed of coarse and fine resistors 有权
标题翻译：由粗细和电阻器形成的裸片终端
公开(公告)号：US07973552B2
公开(公告)日：2011-07-05
申请号：US11950419
申请日：2007-12-04
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H01L27/0802 , H01L28/20
摘要： An integrated circuit includes a semiconductor substrate; a first node; a second node; and a first plurality of resistors, each in a first plurality of resistor units. Each of the first plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The integrated circuit further includes a second plurality of resistors, each in a second plurality of resistor units. Each of the second plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The first plurality of resistors is formed of a first material. The second plurality of resistors is formed of a second material different from the first material. The integrated circuit further includes a switch in one of the first and the second plurality of resistor units and serially connected to a resistor.
摘要翻译：集成电路包括半导体衬底; 第一个节点; 第二个节点; 以及第一多个电阻器，每个在第一多个电阻器单元中。第一多个电阻器单元中的每一个包括连接到第一节点的第一端和连接到第二节点的第二端。集成电路还包括第二多个电阻器，每个电阻器在第二多个电阻器单元中。第二多个电阻器单元中的每一个包括连接到第一节点的第一端和连接到第二节点的第二端。第一多个电阻器由第一材料形成。第二多个电阻器由不同于第一材料的第二材料形成。集成电路还包括在第一和第二多个电阻器单元之一中的开关，并且串联连接到电阻器。

13. 发明授权

US07692442B2 Apparatus for detecting a current and temperature for an integrated circuit 有权
标题翻译：用于检测集成电路的电流和温度的装置
公开(公告)号：US07692442B2
公开(公告)日：2010-04-06
申请号：US11281142
申请日：2005-11-17
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： G01R31/26
CPC分类号： G01R31/025 , G01K7/015 , G01R19/0092 , G01R31/2621 , G01R31/2628
摘要： The present invention discloses an apparatus for detecting a current flowing from a first node to a second node. One or more MOS devices are serially coupled between the first and second nodes. Each of the MOS devices has its body connected to its source and its gate connected to its drain for providing each MOS device with a voltage difference between its gate and its source that is lower than a threshold voltage of the same, such that a voltage difference measured between the first and second nodes responds to a change of the current exponentially.
摘要翻译：本发明公开了一种用于检测从第一节点流向第二节点的电流的装置。一个或多个MOS器件串联耦合在第一和第二节点之间。每个MOS器件的主体连接到其源极，并且其栅极连接到其漏极，以为每个MOS器件提供其栅极和源极之间的电压差低于其栅极电压，使得电压差在第一和第二节点之间测量响应于当前指数变化。

14. 发明授权

US07501884B2 Capacitive circuit employing low voltage MOSFETs and method of manufacturing same 有权
标题翻译：采用低压MOSFET的电容电路及其制造方法
公开(公告)号：US07501884B2
公开(公告)日：2009-03-10
申请号：US10866155
申请日：2004-06-11
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： G01F1/10 , G01F3/00
CPC分类号： H01L27/0811 , H01L27/0629 , H03H7/25
摘要： Disclosed herein are a capacitive circuit for use on a semiconductor substrate, and related method of manufacturing the same. In one aspect, the capacitive circuit includes a plurality of MOSFETs each having their respective source and drain electrically coupled together, where the plurality of MOSFETs are series-coupled to each other by electrically coupling a gate of one of the plurality to the coupled source/drain of another of the plurality. In this embodiment, the circuit also includes a power supply electrically coupled to the plurality of MOSFETs, where a coupled source/drain of one of the plurality of MOSFETs at a first end of the series is electrically coupled to a first terminal of the power supply, and a gate of another of the plurality of MOSFETs at a second end of the series is electrically coupled to a second terminal of the power supply. The circuit also includes a plurality of resistive elements each electrically parallel-coupled across corresponding ones of the plurality of MOSFETs.
摘要翻译：这里公开了用于半导体衬底的电容电路及其制造方法。在一个方面中，电容电路包括多个MOSFET，它们各自具有电耦合在一起的源极和漏极，其中通过将多个MOSFET中的一个的栅极电耦合到耦合的源极/漏极的多个MOSFET彼此串联耦合，多余的另一个的排水。在该实施例中，电路还包括电耦合到多个MOSFET的电源，其中在该串联的第一端的多个MOSFET中的一个MOSFET的耦合源极/漏极电耦合到电源的第一端子并且在该串联的第二端的多个MOSFET中另一个的栅极电耦合到电源的第二端子。电路还包括多个电阻元件，每个电阻元件电平行耦合在多个MOSFET中的相应的MOSFET上。

15. 外观设计

USD537065S1 Telephone 有权
公开(公告)号：USD537065S1
公开(公告)日：2007-02-20
申请号：US29236085
申请日：2005-09-16
申请人： Chung-Hui Chen
设计人： Chung-Hui Chen

16. 发明申请

US20070011538A1 CIRCUIT AND METHOD FOR PERFORMING BUILT-IN SELF TEST AND COMPUTER READABLE RECORDING MEDIUM FOR STORING PROGRAM THEREOF 有权
标题翻译：用于执行内置自检的电路和方法及其存储程序的计算机可读记录介质
公开(公告)号：US20070011538A1
公开(公告)日：2007-01-11
申请号：US11160102
申请日：2005-06-09
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G11C29/16
摘要： A circuit and a method for built-in self test (BIST) and a computer readable recording medium for storing program thereof are provided. The BIST circuit serves a system to self test a circuit-under-test in the system. The system further includes a unit circuit having a plurality of input terminal couple to a plurality of signal path respectively, and an output terminal couple to the circuit-under-test. A selection and activation circuit of the BIST circuit having an output terminal couple to one of input terminals of the unit circuit, one input terminal couple to a non-timing-critical path of the signal paths, and the other input terminal receives a test signal. When the system operates in a test mode, the BIST controller provides the test signal through the selection and activation circuit and the unit circuit to test the circuit-under-test.
摘要翻译：提供了一种用于内置自检（BIST）的电路和方法以及用于存储程序的计算机可读记录介质。 BIST电路用于系统自我测试系统中的电路不足。该系统还包括具有分别耦合到多个信号路径的多个输入端子的单元电路，以及耦合到被测电路的输出端子。 BIST电路的选择和激活电路具有耦合到单元电路的一个输入端的输出端子，耦合到信号路径的非定时关键路径的一个输入端子和另一个输入端子接收测试信号。当系统在测试模式下工作时，BIST控制器通过选择和激活电路和单元电路提供测试信号，以测试电路不足。

17. 发明申请

US20050127946A1 PIPELINE-BASED CIRCUIT WITH A POSTPONED CLOCK-GATING MECHANISM FOR REDUCING POWER CONSUMPTION AND RELATED DRIVING METHOD THEREOF 失效
标题翻译：具有用于降低功耗的后置时钟控制机构的基于管道的电路及其相关驱动方法
公开(公告)号：US20050127946A1
公开(公告)日：2005-06-16
申请号：US10707455
申请日：2003-12-16
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： G06F1/32 , G06F9/38 , H03K19/00
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： A pipeline-based circuit with a postponed clock-gating mechanism and related driving method are disclosed for reducing power consumption, and the driving method does not deteriorate processing performance of the pipeline-based circuit. A pipeline-based circuit has a plurality of logic operators cascaded to form at least a pipeline, a pipeline control unit for generating at least a control signal to each logic operator for controlling whether one logic operator needs to pipe data to next logic operator, and a control value calculator for setting a valid bit of each logic operator following a currently activated logic operator according to the control signals generated from the pipeline control unit. When each logic operator begins operating, the related control value is used to determine whether or not a clock signal piping data of the present logic operator to next logic operator is gated to reduce power consumption. This postponed clock-gating mechanism avoids the degradation of pipeline clock speed limitation.
摘要翻译：公开了一种具有推迟时钟门控机构和相关驱动方法的基于管线的电路，用于降低功耗，并且驱动方法不会降低基于管线的电路的处理性能。基于流水线的电路具有级联的多个逻辑运算器以形成至少一个流水线，流水线控制单元，用于至少向每个逻辑运算器生成控制信号，以控制一个逻辑运算符是否需要将数据传送到下一个逻辑运算符;以及控制值计算器，用于根据从流水线控制单元产生的控制信号，设置当前激活的逻辑运算符之后的每个逻辑运算符的有效位。当每个逻辑运算符开始运行时，相关的控制值用于确定当前逻辑运算符到下一个逻辑运算符的时钟信号管道数据是否被门控以降低功耗。这种推迟的时钟门控机制避免了流水线时钟速度限制的恶化。

18. 发明授权

US06489828B1 Level shifter for ultra-deep submicron CMOS designs 有权
公开(公告)号：US06489828B1
公开(公告)日：2002-12-03
申请号：US10156626
申请日：2002-05-28
申请人： Wen-Tai Wang , Chung-Hui Chen
发明人： Wen-Tai Wang , Chung-Hui Chen
IPC分类号： H03L500
CPC分类号： H03K3/012 , H03K3/356113 , H03K3/356182
摘要： New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output. A third NMOS transistor has the gate tied to the first NMOS drain, v source tied to the level shifting input, and the drain tied to the level shifting output. A fourth NMOS transistor has the gate tied to the second NMOS drain, the source tied to the inverted level shifting input, and the drain tied to the first NMOS drain.

19. 发明授权

US06477604B1 Computer multi-bay devices compatible expansion module and its processing procedure 有权
标题翻译：计算机多机架兼容扩展模块及其处理程序
公开(公告)号：US06477604B1
公开(公告)日：2002-11-05
申请号：US09531432
申请日：2000-03-20
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： G06F1300
CPC分类号： G06F1/1632
摘要： A computer multi-bay devices compatible expansion module includes a housing defining a chamber for receiving a notebook computer multi-bay compatible device, for example, a CD-ROM, DVD-ROM, hard disk driver, or chargeable battery, a set of control buttons, a control circuit board disposed inside the chamber in the housing and controlled by the control buttons to operate the notebook computer multi-bay compatible device being inserted into the chamber in the housing, so as to play a music CD, game CD or DVD, access hard disk data, or charge a chargeable battery.
摘要翻译：一种计算机多间隔设备兼容的扩展模块包括限定用于接收笔记本计算机多机架兼容设备（例如CD-ROM，DVD-ROM，硬盘驱动器或可充电电池）的室的外壳，一组控制按钮，控制电路板，其设置在所述壳体内的所述室内并由所述控制按钮控制以操作将所述笔记本计算机多机架兼容设备插入所述壳体中的所述室中，以便播放音乐CD，游戏CD或DVD ，访问硬盘数据，或为可充电电池充电。

20. 发明授权

US09412883B2 Methods and apparatus for MOS capacitors in replacement gate process 有权
标题翻译：替代栅极工艺中MOS电容器的方法和装置
公开(公告)号：US09412883B2
公开(公告)日：2016-08-09
申请号：US13303083
申请日：2011-11-22
申请人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
发明人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
IPC分类号： H01L29/94 , H01L27/06 , H01L27/08 , H01L49/02
CPC分类号： H01L21/822 , H01L27/0629 , H01L27/0811 , H01L28/20 , H01L29/401 , H01L29/94
摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.
摘要翻译：替代栅极工艺中多晶硅MOS电容器的方法和装置。一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。公开了通过该方法制造的装置。

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