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11. 发明授权

US06539072B1 Delay locked loop circuitry for clock delay adjustment 有权
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US06539072B1
公开(公告)日：2003-03-25
申请号：US09524402
申请日：2000-03-13
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC分类号： H04L700
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.
摘要翻译：延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

12. 发明授权

US6125157A Delay-locked loop circuitry for clock delay adjustment 失效
标题翻译：用于时钟延迟调整的延迟锁定环路
公开(公告)号：US6125157A
公开(公告)日：2000-09-26
申请号：US795657
申请日：1997-02-06
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark
IPC分类号： G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H03L7/081 , H04L7/00
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0037 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H04L7/0008 , H04L7/0025
摘要： Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used.
摘要翻译：延迟锁定环路电路，用于在一对时钟之间产生预定的相位关系。第一延迟锁定环包括布置在链中的一组延迟产生元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。根据使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

13. 发明授权

US5945862A Circuitry for the delay adjustment of a clock signal 失效
标题翻译：电路用于时钟信号的延迟调整
公开(公告)号：US5945862A
公开(公告)日：1999-08-31
申请号：US904203
申请日：1997-07-31
申请人： Kevin S. Donnelly , Jun Kim , Bruno W. Garlepp , Mark A. Horowitz , Thomas H. Lee , Pak Shing Chau , Jared L. Zerbe , Clemenz L. Portmann , Yiu-Fai Chan
发明人： Kevin S. Donnelly , Jun Kim , Bruno W. Garlepp , Mark A. Horowitz , Thomas H. Lee , Pak Shing Chau , Jared L. Zerbe , Clemenz L. Portmann , Yiu-Fai Chan
IPC分类号： H03K5/13 , H03H11/26
CPC分类号： H03K5/1565 , H03K5/13
摘要： Circuitry for adjusting the phase of an incoming periodic signal, typically a clock signal, throughout the entire period of the periodic signal. Phase adjustment circuitry has high resolution and employs only the number of delay elements in a delay chain necessary to span at least the period of the incoming signal or at least half the period in the case of dual chains receiving complementary clocks. Phase adjustment circuitry includes a delay chain of having a plurality of taps, a boundary detector for indicating when a tap is at a phase boundary of the incoming periodic signal, and selection circuitry for selecting one of the taps from the delay chain based on the boundary detector output and the selection circuitry input such that the selected tap is the desired phase adjustment of the incoming periodic signal and that the delay of the incoming signal is adjustable across its phase boundaries. Phase interpolation between the taps of the delay chain is employed to increase the resolution of the adjustment to the periodic signal. Duty cycle correction of the input clock and the selected output clock is employed to improve accuracy.
摘要翻译：用于在整个周期信号的整个周期内调整进入周期信号（通常为时钟信号）的相位的电路。相位调整电路具有高分辨率，并且仅在延迟链中仅使用延伸元件的数量来跨越至少输入信号的周期，或者在双链接收互补时钟的情况下至少半个周期。相位调整电路包括具有多个抽头的延迟链，边界检测器，用于指示抽头何时处于输入周期性信号的相位边界;以及选择电路，用于基于边界从延迟链中选择一个抽头检测器输出和选择电路输入，使得所选择的抽头是输入周期性信号的期望的相位调整，并且输入信号的延迟在其相位边界上是可调节的。使用延迟链的抽头之间的相位插值来增加对周期性信号的调整的分辨率。采用输入时钟和选择的输出时钟的占空比校正来提高精度。

14. 发明授权

US07337294B2 Method and apparatus for adjusting the performance of a synchronous memory system 有权
标题翻译：用于调整同步存储器系统性能的方法和装置
公开(公告)号：US07337294B2
公开(公告)日：2008-02-26
申请号：US11609135
申请日：2006-12-11
申请人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
发明人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
IPC分类号： G06F13/16
CPC分类号： G11C7/1048 , G06F13/1689 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.
摘要翻译：提供了一种用于调整存储器系统的性能的方法和装置。存储器系统包括主设备和从设备。存储器通道将主设备耦合到从设备，使得从设备经由存储器通道从主设备接收系统操作信息。从设备还包括用于在从设备内调谐电路的装置，从而提高存储器系统的性能。

15. 发明授权

US07134101B2 Active impedance compensation 有权
公开(公告)号：US07134101B2
公开(公告)日：2006-11-07
申请号：US10346859
申请日：2003-01-16
申请人： Haw-Jyh Liaw , Donald V. Perino , Pak Shing Chau , Kevin S. Donnelly
发明人： Haw-Jyh Liaw , Donald V. Perino , Pak Shing Chau , Kevin S. Donnelly
IPC分类号： G06F17/50
CPC分类号： G06F13/4086
摘要： Active impedance compensation is accomplished in a bus system by means of a variable capacitor element associated with a connection circuit between system slave devices and an impedance balanced channel. The variable capacitor elements may be programmed using a control value determined by actively exercising the channel with a telemetry signal and evaluating the resulting signal reflections which are indicative of the impedance discontinuities on the channel.

16. 发明授权

US6133773A Variable delay element 失效
标题翻译：可变延迟元件
公开(公告)号：US6133773A
公开(公告)日：2000-10-17
申请号：US947477
申请日：1997-10-10
申请人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Leung Yu , Benedict Chung-Kwong Lau , Roxanne Vu
发明人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Leung Yu , Benedict Chung-Kwong Lau , Roxanne Vu
IPC分类号： H03K5/00 , H03K5/13 , H03H11/16
CPC分类号： H03K5/13 , H03K2005/00065 , H03K2005/00071 , H03K2005/00163 , H03K2005/00202 , H03K2005/00208 , H03K2005/00286
摘要： A method and apparatus for an adjustable phase interpolator is provided. The adjustable phase interpolator includes a phase interpolator circuit that has a voltage input and a voltage output. The adjustable phase interpolator further includes a controllable capacitive load coupled to either the input or the output of the phase interpolator circuit. The controllable capacitive load is designed to add or subtract capacitance to the adjustable phase interpolator.
摘要翻译：提供了一种用于可调相位内插器的方法和装置。可调相位内插器包括具有电压输入和电压输出的相位内插器电路。可调相位内插器还包括耦合到相位内插器电路的输入或输出的可控容性负载。可控容性负载被设计为向可调相位内插器增加或减去电容。

17. 发明授权

US07308065B2 Delay locked loop circuitry for clock delay adjustment 失效
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US07308065B2
公开(公告)日：2007-12-11
申请号：US11406557
申请日：2006-04-18
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC分类号： H03D3/24 , H03L7/06
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
摘要翻译：适于耦合到数据总线并被配置为根据接收时钟接收数据的接收机包括第一和第二延迟锁定环路。第一延迟锁定环路被配置为从第一参考时钟产生多个相位矢量，并且第二延迟锁定环路耦合到第一延迟锁定环路并且被配置为从至少一个相位矢量生成接收时钟从所述多个相位矢量中选择并具有第二参考时钟。

18. 发明授权

US07149856B2 Method and apparatus for adjusting the performance of a synchronous memory system 失效
公开(公告)号：US07149856B2
公开(公告)日：2006-12-12
申请号：US10386210
申请日：2003-03-10
申请人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
发明人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
IPC分类号： G06F13/00
CPC分类号： G11C7/1048 , G06F13/1689 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.

19. 再颁专利

USRE37452E1 At frequency phase shifting circuit for use in a quadrature clock generator 有权
标题翻译：用于正交时钟发生器的频率移相电路
公开(公告)号：USRE37452E1
公开(公告)日：2001-11-20
申请号：US09654861
申请日：2000-09-01
申请人： Kevin S. Donnelly , Pak Shing Chau
发明人： Kevin S. Donnelly , Pak Shing Chau
IPC分类号： H03H1116
CPC分类号： H03L7/0812 , H03H11/18 , H03K5/133 , H03K5/151 , H03K2005/00208
摘要： A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.
摘要翻译：可用作正交时钟发生器的一部分的移相电路。相移电路包括耦合以接收输入参考信号的三角波发生器。三角波发生器响应于输入参考信号输出一对互补三角波信号。具有一对输入的比较器被耦合以接收该对互补三角波信号。响应于一对互补三角波信号之间的比较，比较器输出与输入参考信号具有预定相位关系的输出信号。

20. 发明授权

US5808498A At frequency phase shifting circuit for use in a quadrature clock generator 失效
标题翻译：用于正交时钟发生器的频率移相电路
公开(公告)号：US5808498A
公开(公告)日：1998-09-15
申请号：US891128
申请日：1997-07-10
申请人： Kevin S. Donnelly , Pak Shing Chau
发明人： Kevin S. Donnelly , Pak Shing Chau
IPC分类号： H03K5/15 , H03H11/18 , H03K5/00 , H03K5/13 , H03K5/151 , H03L7/081 , H03H11/16
CPC分类号： H03L7/0812 , H03H11/18 , H03K5/133 , H03K5/151 , H03K2005/00208
摘要： A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.
摘要翻译：可用作正交时钟发生器的一部分的移相电路。相移电路包括耦合以接收输入参考信号的三角波发生器。三角波发生器响应于输入参考信号输出一对互补三角波信号。具有一对输入的比较器被耦合以接收该对互补三角波信号。响应于一对互补三角波信号之间的比较，比较器输出与输入参考信号具有预定相位关系的输出信号。

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