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11. 发明申请

US20100086094A1 Delay-Locked loop With Dynamically Biased Charge Pump 审中-公开
标题翻译：具有动态偏置电荷泵的延迟锁定环
公开(公告)号：US20100086094A1
公开(公告)日：2010-04-08
申请号：US12634596
申请日：2009-12-09
申请人： John George Maneatis , Jaeha Kim , Daniel Karl Hartman
发明人： John George Maneatis , Jaeha Kim , Daniel Karl Hartman
IPC分类号： H03D3/24
CPC分类号： H03L7/089 , H03L7/07 , H03L7/08 , H03L7/0812 , H03L7/0895 , H03L7/0896
摘要： A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.
摘要翻译：一种延迟锁定环路，包括配置为接收两个信号的相位检测器，其中一个信号相对于另一个信号被延迟，相位检测器具有UP输出和DOWN输出。延迟锁定回路还包括与相位检测器可操作地耦合的电荷泵系统，电荷泵系统包括（1）电荷泵，其被配置为响应于来自UP输出和DOWN输出的致动信号的断言，以便控制从电荷泵系统抽取电荷，这种泵送电荷可用于控制承载两个信号之一的延迟线，以便控制在两个信号之间发生的相对延迟; 以及（2）反馈控制回路，其被配置为在电荷泵处动态地调整至少一个偏置信号，以便在同时断言来自UP输出和DOWN输出的致动信号的同时最小化从电荷泵系统泵送的净电荷。

12. 发明授权

US07627044B2 Clock-edge modulated serial link with DC-balance control 有权
标题翻译：具有直流平衡控制的时钟调制串行链路
公开(公告)号：US07627044B2
公开(公告)日：2009-12-01
申请号：US11264303
申请日：2005-10-31
申请人： Gyudong Kim , Won Jun Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
发明人： Gyudong Kim , Won Jun Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
IPC分类号： H04B3/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
摘要翻译：电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被配置为恢复直流平衡控制信号。

13. 发明授权

US07602253B2 Adaptive bandwidth phase locked loop with feedforward divider 有权
标题翻译：带前馈分频器的自适应带宽锁相环
公开(公告)号：US07602253B2
公开(公告)日：2009-10-13
申请号：US11637254
申请日：2006-12-11
申请人： Jaeha Kim , Deog-Kyoon Jeong
发明人： Jaeha Kim , Deog-Kyoon Jeong
IPC分类号： H03L7/00
CPC分类号： H03L7/23 , H03L7/0895 , H03L7/093 , H03L7/0995
摘要： In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括第一和第二子锁相环（sub-PLL），其包括第一和第二压控振荡器（VCO），以提供第一和第二VCO输出信号，以及第一和第二前馈分配器电路以分开第一和第二频率的第一和第二VCO输出信号通过第一和第二分频因子。该芯片还包括用于选择第一和第二分频因子的锁相环控制电路。描述和要求保护其他实施例。

14. 发明申请

US20080136531A1 Adaptive bandwidth phase locked loop with feedforward divider 有权
标题翻译：带前馈分频器的自适应带宽锁相环
公开(公告)号：US20080136531A1
公开(公告)日：2008-06-12
申请号：US11637254
申请日：2006-12-11
申请人： Jaeha Kim , Deog-Kyoon Jeong
发明人： Jaeha Kim , Deog-Kyoon Jeong
IPC分类号： H03L7/07
CPC分类号： H03L7/23 , H03L7/0895 , H03L7/093 , H03L7/0995
摘要： In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括第一和第二子锁相环（sub-PLL），其包括第一和第二压控振荡器（VCO），以提供第一和第二VCO输出信号，以及第一和第二前馈分配器电路以分开第一和第二频率的第一和第二VCO输出信号通过第一和第二分频因子。该芯片还包括用于选择第一和第二分频因子的锁相环控制电路。描述和要求保护其他实施例。

15. 发明授权

US08929496B2 Receiver with enhanced clock and data recovery 有权
标题翻译：接收机具有增强的时钟和数据恢复功能
公开(公告)号：US08929496B2
公开(公告)日：2015-01-06
申请号：US12812720
申请日：2009-01-30
申请人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
发明人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
IPC分类号： H04L7/00 , H04L7/033 , H04L25/06 , H04L25/03 , H04L27/00
CPC分类号： H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
摘要： A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
摘要翻译：接收机设备利用基于边缘的时钟和数据恢复来实现增强的数据接收，例如使用闪存模数转换器架构。在示例实施例中，设备实现第一相位调节控制回路，例如，一个爆炸相位检测器，其通过调整边沿时钟的相位来检测数据转换以便在边缘采样器的最优边缘时间调整采样的采样器。该循环可以通过调整诸如闪存ADC的数据采样器的数据时钟的相位来进一步调整接收数据间隔中的采样以实现最佳数据接收。该装置还可以实现具有例如波特率相位检测器的第二相位调整控制回路，波形率相位检测器检测数据间隔以便在数据采样器的最佳数据时间进一步调整采样。

16. 发明授权

US08422590B2 Apparatus and methods for differential signal receiving 有权
标题翻译：差分信号接收的装置和方法
公开(公告)号：US08422590B2
公开(公告)日：2013-04-16
申请号：US12746018
申请日：2008-10-29
申请人： Brian S. Leibowitz , Jaeha Kim , Hae-Chang Lee
发明人： Brian S. Leibowitz , Jaeha Kim , Hae-Chang Lee
IPC分类号： H04L27/00
CPC分类号： H04L7/0338 , H03K5/133 , H04L7/0008
摘要： A differential signal receiver 106 implements intra-pair skew compensation for improving data transfer on a differential channel. In an embodiment, the receiver implements sampling by—multiple clocks with different phases such that the signals of the differential channel may be separately or individually time adjusted to account for skew between them so that they may be differentially compared for data resolution. In one embodiment, a positive sampler and negative sampler are controlled by distinct clock signals to permit, at different times, sampling and holding of the positive and negative signals representing a data bit on the differential channel. A differential decision circuit may then differentially resolve the data using a latter one of the distinct clock signals. Timing generation circuitry for producing the offset clocks may include a skew detector that permits dynamic adjustment of the different clock signals according to skew associated with the signals of the differential channel.
摘要翻译：差分信号接收机106实现对对偏斜补偿，以改善差分信道上的数据传输。在一个实施例中，接收机以不同的相位实现采样多个时钟，使得差分信道的信号可以单独地或单独地进行时间调整以解决它们之间的偏斜，使得它们可以被差分地比较用于数据分辨率。在一个实施例中，正采样器和负采样器由不同的时钟信号控制，以允许在不同时间对表示差分信道上的数据位的正和负信号进行采样和保持。然后差分判决电路可以使用不同时钟信号中的后一个来差分地解析数据。用于产生偏移时钟的定时发生电路可以包括偏斜检测器，其允许根据与差分信道的信号相关联的偏斜动态调整不同的时钟信号。

17. 发明授权

US08155174B2 Hardware and method to test phase linearity of phase synthesizer 失效
标题翻译：测试相位合成器相位线性的硬件和方法
公开(公告)号：US08155174B2
公开(公告)日：2012-04-10
申请号：US12531830
申请日：2008-03-14
申请人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
发明人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
IPC分类号： H04B3/46
CPC分类号： H03M1/109 , G01R31/31725 , G01R31/31726 , G01R31/31727 , H03M1/66
摘要： A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output.
摘要翻译：用于测试相位合成器的相位线性度的电路，其合成具有相应于输入到相位合成器的数字相位值的相位的输出时钟。数字计数器向相位合成器提供数字相位值。数字计数器接收与输入时钟同步的计数器时钟。数字相位值由数字计数器步进，从而移位输出时钟的频率。对相位合成器的相位线性度分析输出时钟，以产生相位线性分析输出。

18. 发明申请

US20110228616A1 Clock Generator Circuits with Non-Volatile Memory for Storing and/or Feedback-Controlling Phase and Frequency 有权
标题翻译：具有用于存储和/或反馈控制相位和频率的非易失性存储器的时钟发生器电路
公开(公告)号：US20110228616A1
公开(公告)日：2011-09-22
申请号：US12674598
申请日：2008-08-22
申请人： Jaeha Kim , Brent Haukness
发明人： Jaeha Kim , Brent Haukness
IPC分类号： G11C8/18 , G11C7/00
CPC分类号： H03L7/187 , H03L7/0812 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/10 , H03L2207/08
摘要： A clock-signal generator (e.g. a PLL or a DLL) uses non-volatile memory to store an analog control voltage that determines an output phase and/or frequency of the clock-signal generator. Locked loops take time to lock on a given reference frequency. To keep this time to a minimum, NVM 105 stores the control voltage during periods of inactivity, such as when the signal generator is powered down or in a standby mode. Non-volatile memory stores control voltages during operation in other embodiments to relax the area requirements otherwise required for integration capacitors to store phase and frequency information.
摘要翻译：时钟信号发生器（例如PLL或DLL）使用非易失性存储器来存储确定时钟信号发生器的输出相位和/或频率的模拟控制电压。锁定环路需要时间来锁定给定的参考频率。为了将此时间保持在最低限度，NVM105在不活动期间存储控制电压，例如当信号发生器断电或处于待机模式时。非易失性存储器在其他实施例中在操作期间存储控制电压，以放松否则为积分电容器存储相位和频率信息所需的面积要求。

19. 发明申请

US20100289544A1 Receiver With Enhanced Clock And Data Recovery 有权
标题翻译：接收机具有增强的时钟和数据恢复功能
公开(公告)号：US20100289544A1
公开(公告)日：2010-11-18
申请号：US12812720
申请日：2009-01-30
申请人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
发明人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
IPC分类号： H03L7/06
CPC分类号： H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
摘要： A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
摘要翻译：接收机设备利用基于边缘的时钟和数据恢复来实现增强的数据接收，例如使用闪存模数转换器架构。在示例实施例中，设备实现第一相位调节控制回路，例如，一个爆炸相位检测器，其通过调整边沿时钟的相位来检测数据转换以便在边缘采样器的最优边缘时间调整采样的采样器。该循环可以通过调整诸如闪存ADC的数据采样器的数据时钟的相位来进一步调整接收数据间隔中的采样以实现最佳数据接收。该装置还可以实现具有例如波特率相位检测器的第二相位调整控制回路，波形率相位检测器检测数据间隔以便在数据采样器的最佳数据时间进一步调整采样。

20. 发明授权

US07634039B2 Delay-locked loop with dynamically biased charge pump 有权
标题翻译：具有动态偏置电荷泵的延迟锁定回路
公开(公告)号：US07634039B2
公开(公告)日：2009-12-15
申请号：US11347835
申请日：2006-02-03
申请人： John George Maneatis , Jaeha Kim , Daniel Karl Hartman
发明人： John George Maneatis , Jaeha Kim , Daniel Karl Hartman
IPC分类号： H03D3/24
CPC分类号： H03L7/089 , H03L7/07 , H03L7/08 , H03L7/0812 , H03L7/0895 , H03L7/0896
摘要： A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.
摘要翻译：一种延迟锁定环路，包括配置为接收两个信号的相位检测器，其中一个信号相对于另一个信号被延迟，相位检测器具有UP输出和DOWN输出。延迟锁定回路还包括与相位检测器可操作地耦合的电荷泵系统，电荷泵系统包括（1）电荷泵，其被配置为响应于来自UP输出和DOWN输出的致动信号的断言，以便控制从电荷泵系统抽取电荷，这种泵送电荷可用于控制承载两个信号之一的延迟线，以便控制在两个信号之间发生的相对延迟; 以及（2）反馈控制回路，其被配置为在电荷泵处动态地调整至少一个偏置信号，以便在同时断言来自UP输出和DOWN输出的致动信号的同时最小化从电荷泵系统泵送的净电荷。

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