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1. 发明申请

US20100102868A1 Hardware and Method to Test Phase Linearity of Phase Synthesizer 失效
标题翻译：测试相位合成器的相位线性度的硬件和方法
公开(公告)号：US20100102868A1
公开(公告)日：2010-04-29
申请号：US12531830
申请日：2008-03-14
申请人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
发明人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
IPC分类号： G06F1/04
CPC分类号： H03M1/109 , G01R31/31725 , G01R31/31726 , G01R31/31727 , H03M1/66
摘要： A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output.
摘要翻译：用于测试相位合成器的相位线性度的电路，其合成具有相应于输入到相位合成器的数字相位值的相位的输出时钟。数字计数器向相位合成器提供数字相位值。数字计数器接收与输入时钟同步的计数器时钟。数字相位值由数字计数器步进，从而移位输出时钟的频率。对相位合成器的相位线性度分析输出时钟，以产生相位线性分析输出。

2. 发明授权

US08155174B2 Hardware and method to test phase linearity of phase synthesizer 失效
标题翻译：测试相位合成器相位线性的硬件和方法
公开(公告)号：US08155174B2
公开(公告)日：2012-04-10
申请号：US12531830
申请日：2008-03-14
申请人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
发明人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
IPC分类号： H04B3/46
CPC分类号： H03M1/109 , G01R31/31725 , G01R31/31726 , G01R31/31727 , H03M1/66
摘要： A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output.
摘要翻译：用于测试相位合成器的相位线性度的电路，其合成具有相应于输入到相位合成器的数字相位值的相位的输出时钟。数字计数器向相位合成器提供数字相位值。数字计数器接收与输入时钟同步的计数器时钟。数字相位值由数字计数器步进，从而移位输出时钟的频率。对相位合成器的相位线性度分析输出时钟，以产生相位线性分析输出。

3. 发明申请

US20100090732A1 CLOCK AND DATA RECOVERY EMPLOYING PIECE-WISE ESTIMATION ON THE DERIVATIVE OF THE FREQUENCY 有权
标题翻译：时钟和数据恢复在频率的衍生中使用一个简单的估计
公开(公告)号：US20100090732A1
公开(公告)日：2010-04-15
申请号：US12441003
申请日：2007-09-05
申请人： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
发明人： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
IPC分类号： H03L7/00
CPC分类号： H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
摘要： A system and method for performing clock data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.
摘要翻译：一种用于执行时钟数据恢复的系统和方法。系统根据数据发送器时钟的频率和接收机时钟15的频率之间的偏移的变化率的至少三个估计来设置恢复的时钟信号30的相位。

4. 发明授权

US08311176B2 Clock and data recovery employing piece-wise estimation on the derivative of the frequency 有权
标题翻译：使用对频率导数进行分段估计的时钟和数据恢复
公开(公告)号：US08311176B2
公开(公告)日：2012-11-13
申请号：US12441003
申请日：2007-09-05
申请人： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
发明人： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
IPC分类号： H03D3/24
CPC分类号： H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
摘要： A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.
摘要翻译：一种用于执行时钟和数据恢复的系统和方法。系统根据数据发送器时钟的频率和接收机时钟15的频率之间的偏移的变化率的至少三个估计来设置恢复的时钟信号30的相位。

5. 发明申请

US20130136220A1 Clock and Data Recovery Employing Piece-Wise Estimation on the Derivative of the Frequency 有权
标题翻译：时钟和数据恢复采用对频率微分的智慧估计
公开(公告)号：US20130136220A1
公开(公告)日：2013-05-30
申请号：US13674812
申请日：2012-11-12
申请人： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
发明人： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
摘要： A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.
摘要翻译：一种用于执行时钟和数据恢复的系统和方法。根据数据发送器时钟的频率和接收机时钟的频率之间的偏移的变化率的至少三个估计，系统设置恢复的时钟信号的相位。

6. 发明授权

US08279976B2 Signaling with superimposed differential-mode and common-mode signals 有权
标题翻译：信号叠加差分模式和共模信号
公开(公告)号：US08279976B2
公开(公告)日：2012-10-02
申请号：US12739938
申请日：2008-10-28
申请人： Qi Lin , Hae-Chang Lee , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Hae-Chang Lee , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H03K9/00
CPC分类号： H04L25/0272 , H04L5/20 , H04L25/0262
摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
摘要翻译：数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。第一和第二相应的传输线包括数据接收器电路外部的一对传输线。第一和第二接口从一对传输线接收传输信号。共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。提取的数据信号具有与提取的时钟信号的频率相对应的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。差分模式电路与提取的时钟信号同步。

7. 发明申请

US20100085123A1 INJECTION-LOCKED CLOCK MULTIPLIER 审中-公开
标题翻译：注射锁定时间累加器
公开(公告)号：US20100085123A1
公开(公告)日：2010-04-08
申请号：US12577027
申请日：2009-10-09
申请人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Jaeha Kim
发明人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Jaeha Kim
IPC分类号： H03L7/24
CPC分类号： H03L7/083 , H03L7/099 , H03L7/18
摘要： Embodiments of a clock circuit are described. This clock circuit includes an oscillator, which includes a resonance circuit having a resonance frequency, that outputs a first clock signal having a first frequency. Furthermore, a digital controller is coupled to the oscillator. This digital controller modifies the resonance frequency of the oscillator during a first mode of operation of the clock circuit, and the modifying is ceased during a second mode of operation of the clock circuit. In addition, on injection circuit is coupled to the oscillator. This injection circuit provides a second clock signal having a second frequency to the oscillator. Note that the second clock signal injection locks a phase and/or the first frequency of the first clock signal. Also note that a ratio of the first frequency to the second frequency is greater than or equal to one.
摘要翻译：描述时钟电路的实施例。该时钟电路包括振荡器，其包括具有谐振频率的谐振电路，该谐振电路输出具有第一频率的第一时钟信号。此外，数字控制器耦合到振荡器。该数字控制器在时钟电路的第一操作模式期间修改振荡器的谐振频率，并且在时钟电路的第二操作模式期间中止修改。另外，注入电路耦合到振荡器。该注入电路向振荡器提供具有第二频率的第二时钟信号。注意，第二时钟信号注入锁定第一时钟信号的相位和/或第一频率。还要注意，第一频率与第二频率的比率大于或等于1。

8. 发明授权

US09423441B2 Integrated circuit having receiver jitter tolerance (“JTOL”) measurement 有权
标题翻译：具有接收机抖动容限（“JTOL”）测量的集成电路
公开(公告)号：US09423441B2
公开(公告)日：2016-08-23
申请号：US13621783
申请日：2012-09-17
申请人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
发明人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC分类号： G01R29/26 , G01R31/317
CPC分类号： G01R29/26 , G01R31/31709 , G01R31/31725
摘要： An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
摘要翻译：能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样。从接收器输出的采样数据值用于评估集成电路的抖动容限。

9. 发明授权

US08289032B2 Integrated circuit having receiver jitter tolerance (“JTOL”) measurement 有权
标题翻译：具有接收机抖动容限（JTOL）测量的集成电路
公开(公告)号：US08289032B2
公开(公告)日：2012-10-16
申请号：US12529320
申请日：2008-03-19
申请人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
发明人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC分类号： G01R29/26
CPC分类号： G01R29/26 , G01R31/31709 , G01R31/31725
摘要： An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
摘要翻译：能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样。从接收器输出的采样数据值用于评估集成电路的抖动容限。

10. 发明申请

US20100097071A1 Integrated Circuit Having Receiver Jitter Tolerance ("JTOL") Measurement 有权
标题翻译：具有接收机抖动容限（“JTOL”）测量的集成电路
公开(公告)号：US20100097071A1
公开(公告)日：2010-04-22
申请号：US12529320
申请日：2008-03-19
申请人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
发明人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC分类号： G01R31/02 , G06F1/04 , G06F11/00
CPC分类号： G01R29/26 , G01R31/31709 , G01R31/31725
摘要： An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
摘要翻译：能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样。从接收器输出的采样数据值用于评估集成电路的抖动容限。

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