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11. 发明授权

US07710179B2 Programmable gain attenuator for track and hold amplifiers 有权
标题翻译：用于跟踪和保持放大器的可编程增益衰减器
公开(公告)号：US07710179B2
公开(公告)日：2010-05-04
申请号：US11341384
申请日：2006-01-30
申请人： Ovidiu Bajdechi , Franciscus Maria Leonardus van der Goes
发明人： Ovidiu Bajdechi , Franciscus Maria Leonardus van der Goes
IPC分类号： H03L5/00
CPC分类号： H03F3/45475 , H03F1/34 , H03F2203/45528 , H03F2203/45534 , H03G1/0088 , H03G3/001
摘要： A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.
摘要翻译：公开了一种特别用于跟踪和保持电路中的可编程增益衰减器（PGA）。 PGA位于运算放大器周围的反馈路径中。一个分接开关用于将一个PGA部分连接到运算放大器的输出。 PGA部分能够通过在分压器中使用多个次级电阻器件来产生多种不同的增益设置，其中每个电阻器件可以独立地耦合到参考电压。

12. 发明授权

US07271755B2 Resistor ladder interpolation for PGA and DAC 失效
标题翻译： PGA和DAC的电阻梯形图插补
公开(公告)号：US07271755B2
公开(公告)日：2007-09-18
申请号：US10926407
申请日：2004-08-26
申请人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Jan Westra , Rudy van der Plassche
发明人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Jan Westra , Rudy van der Plassche
IPC分类号： H03M1/12 , H03M1/78 , G06F17/17
CPC分类号： H03K17/04106 , H03M1/204 , H03M1/365
摘要： A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
摘要翻译：电压内插电路包括连接在地和电压输入端之间的电阻梯形电阻，并具有多个电阻器，电阻器之间具有电压抽头。放大器（可选地）具有在其相应的第一端子和放大器的输入端连接在一起的第一和第二电容器。第一多个开关将各个抽头连接到第一电容器的第二端子。第二多个开关将各个抽头连接到第二电容器的第二端子。通过控制第一和第二多个开关来内插输出电压。

13. 发明申请

US20070182476A1 ISI reduction technique 有权
标题翻译： ISI缩减技术
公开(公告)号：US20070182476A1
公开(公告)日：2007-08-09
申请号：US11523694
申请日：2006-09-20
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward
IPC分类号： G06G7/18
CPC分类号： H03H19/004
摘要： The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.
摘要翻译：本发明涉及信号处理电路，更具体地说，涉及开关电容器电路以及减少符号间干扰的方法。提供了具有减小的符号间干扰效应的开关电容器电路，包括：电压源，第一电容器，第二电容器和至少一个开关，其被配置为以将第一电容器充电到第一电容器电压，然后通过第二电容器放电，从而减少符号间干扰效应。

14. 发明申请

US20050035810A1 Multiplexer with low parasitic capacitance effects 有权
标题翻译：具有低寄生电容效应的多路复用器
公开(公告)号：US20050035810A1
公开(公告)日：2005-02-17
申请号：US10953420
申请日：2004-09-30
申请人： Jan Mulder , Franciscus Maria Leonardus van der Goes
发明人： Jan Mulder , Franciscus Maria Leonardus van der Goes
IPC分类号： H03M1/36 , H03M1/12
CPC分类号： H03K17/002 , H03K17/145 , H03M1/36 , H03M1/365
摘要： A differential multiplexer includes a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes first, second, third and fourth transistors. The first and second transistors input the positive input signal. The third and fourth transistors input the negative input signal. Outputs of the first and third transistors are connected to the positive output signal. Outputs of the second and fourth transistors are connected to the negative output signal. The positive and negative output signals are controlled using gate voltages on the first and fourth transistors. The second and third transistors are turned off when the differential multiplexer is in use. The transistors are cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals.
摘要翻译：差分多路复用器包括多个复用电路。每个复用电路输入包括正输入信号和负输入信号的对应差分输入信号，并输出正和负输出信号。每个复用电路包括第一，第二，第三和第四晶体管。第一和第二晶体管输入正输入信号。第三和第四晶体管输入负输入信号。第一和第三晶体管的输出端连接到正输出信号。第二和第四晶体管的输出端连接到负输出信号。正和负输出信号通过第一和第四晶体管上的栅极电压来控制。当使用差分多路复用器时，第二和第三晶体管截止。晶体管交叉耦合以在正输入信号和负输出信号中的正输入信号和负输入信号共模之间产生泄漏。

15. 发明授权

US07262639B2 High-speed comparator 有权
标题翻译：高速比较器
公开(公告)号：US07262639B2
公开(公告)日：2007-08-28
申请号：US11038388
申请日：2005-01-21
申请人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Marcel Lugthart
发明人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Marcel Lugthart
IPC分类号： H03K5/22
CPC分类号： G01R19/16519 , G01R19/16557 , H03K3/356139 , H03K5/2481 , H03K5/249 , H03M1/0604
摘要： A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.
摘要翻译：差分比较器，具有更低的电源电压，具有改进的误码率性能。差分比较器包括接收差分输入的第一对晶体管。第二对晶体管耦合到第一对晶体管。一对电阻元件连接在第一对和第二对晶体管之间，以增加由第一和第二对晶体管共享的偏置电流。增加的偏置电流减少差分比较器从元稳定状态转变到稳定状态所需的时间，从而提高差分比较器的误码率。电阻元件可以使用线性电阻或传输门。第一或第二对晶体管的栅极可以提供输出。

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