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11. 发明申请

US20080049534A1 Voltage Controlled Static Random Access Memory 失效
标题翻译：电压控制静态随机存取存储器
公开(公告)号：US20080049534A1
公开(公告)日：2008-02-28
申请号：US11923796
申请日：2007-10-25
申请人： John Fifield , Harold Pilo
发明人： John Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C11/413
摘要： A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines(WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.
摘要翻译：一种静态随机存取存储器（SRAM），包括多个SRAM单元，多个字线（WL 0 -WLN）和用于用字线电压信号（VWLP）驱动字线的电压调节器。确定字线电压信号以便减少发生读取干扰和其它存储器不稳定性的可能性。在一个实施例中，字线电压信号被确定为SRAM单元的亚稳态电压（VMETA）的函数，以及作为预定电压余量（VM）的函数的经调整的最正向下电平电压（VAMPDL）对应于SRAM单元的读取 - 干扰电压的正向下电平电压（VMPDL）。

12. 发明申请

US20070229116A1 APPARATUS FOR IMPLEMENTING DYNAMIC DATA PATH WITH INTERLOCKED KEEPER AND RESTORE DEVICES 有权
标题翻译：用于实现动态数据路径的设备，具有互锁的保持和恢复设备
公开(公告)号：US20070229116A1
公开(公告)日：2007-10-04
申请号：US11278169
申请日：2006-03-31
申请人： George Braceras , John Fifield , Harold Pilo
发明人： George Braceras , John Fifield , Harold Pilo
IPC分类号： H03K19/096
CPC分类号： G11C7/1051 , G11C7/1057
摘要： A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second keeper path is configured to maintain the dynamic data path at a nominal precharge level prior to an evaluation thereof, wherein the second keeper path is decoupled from the dynamic data path during the evaluation.
摘要翻译：用于动态逻辑的保持器装置包括静态耦合到动态数据路径的第一保持器路径，第一保持器路径被配置为在其评估期间防止动态数据路径的假放电，以及选择性地耦合到动态数据路径的第二保持器路径。第二保持器路径被配置为在其评估之前将动态数据路径保持在标称预充电水平，其中在评估期间第二保持器路径与动态数据路径解耦。

13. 发明申请

US20070222497A1 METHOD OF IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS 有权
标题翻译：改进半导体应用中保险丝状态检测和电位的方法
公开(公告)号：US20070222497A1
公开(公告)日：2007-09-27
申请号：US11277315
申请日：2006-03-23
申请人： John Barwin , Steven Lamphier , Harold Pilo
发明人： John Barwin , Steven Lamphier , Harold Pilo
IPC分类号： H01H37/76
CPC分类号： G11C17/18 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.
摘要翻译：公开了一种装置的实施例，其包括适于确定所选保险丝的状态的检测电路和用于根据需要吹送选定保险丝的编程电路。此外，公开了相关方法的实施例。检测电路包括相同的信号和参考支路中的多个保险丝，以便增加用于检测熔断熔丝和/或电流源的信号余量，该熔断器和/或电流源被配置为使偏移电流通过信号和参考支路，以便设置用于检测的跳闸点在未吹塑和最小吹塑电阻之间熔断熔断器。因此，本发明提供具有比单面和差分熔丝状态检测装置更高灵敏度的单面熔丝状态检测装置的灵活性。

14. 发明申请

US20070085557A1 METHOD AND APPARATUS FOR BURN-IN OPTIMIZATION 失效
标题翻译：用于烧结优化的方法和装置
公开(公告)号：US20070085557A1
公开(公告)日：2007-04-19
申请号：US11538833
申请日：2006-10-05
申请人： Wagdi Abadeer , Harold Pilo , Daryl Seitzer
发明人： Wagdi Abadeer , Harold Pilo , Daryl Seitzer
IPC分类号： G01R31/26
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.
摘要翻译：本发明提供一种用于优化集成电路的老化的方法和装置。该方法的一个实施例包括：执行集成电路的老化过程的第一部分; 在老化过程的第一部分期间监测集成电路的功耗; 增加老化温度，直到集成电路的功耗达到预定的最大功耗; 以及在增加的老化温度下执行集成电路的老化过程的后续部分。

15. 发明申请

US20070035985A1 VOLTAGE CONTROLLED STATIC RANDOM ACCESS MEMORY 有权
标题翻译：电压控制随机访问存储器
公开(公告)号：US20070035985A1
公开(公告)日：2007-02-15
申请号：US11161742
申请日：2005-08-15
申请人： John Fifield , Harold Pilo
发明人： John Fifield , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C11/413
摘要： A static random access memory (SRAM) (200, 400) comprising a plurality of SRAM cells (204), a plurality of wordlines (WL0-WLN) and a voltage regulator (240, 240′, 300, 516) for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.
摘要翻译：包括多个SRAM单元（204），多个字线（WL 0 -WLN）和用于驱动所述多个SRAM单元的电压调节器（240,240'，300,516）的静态随机存取存储器（SRAM）（200,400）具有字线电压信号（VWLP）的字线。确定字线电压信号以便减少发生读取干扰和其它存储器不稳定性的可能性。在一个实施例中，字线电压信号被确定为SRAM单元的亚稳态电压（VMETA）的函数，以及作为预定电压余量（VM）的函数的经调整的最正向下电平电压（VAMPDL）对应于SRAM单元的读取 - 干扰电压的正向下电平电压（VMPDL）。

16. 发明授权

US06998897B2 System and method for implementing a micro-stepping delay chain for a delay locked loop 有权
标题翻译：用于实现延迟锁定环路的微步延迟链的系统和方法
公开(公告)号：US06998897B2
公开(公告)日：2006-02-14
申请号：US10708311
申请日：2004-02-24
申请人： Harold Pilo , Reid A. Wistort
发明人： Harold Pilo , Reid A. Wistort
IPC分类号： H03H11/26
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03K2005/00221 , H03L7/0818
摘要： A delay locked loop for use in an integrated circuit device includes a coarse delay chain in series with a micro-stepped delay chain. The coarse delay chain includes a plurality of coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and the micro-stepped delay chain is configured for selectively providing a fine delay adjustment with respect to the input clock signal. The micro-stepped delay chain further includes a plurality of parallel signal paths, wherein one or more of the parallel signal paths are capacitively loaded so as to provide the fine delay adjustment.
摘要翻译：用于集成电路器件的延迟锁定环包括与微步延迟链串联的粗延迟链。粗延迟链包括被配置用于相对于输入时钟信号有选择地提供粗延迟的多个粗延迟单元，并且微步延迟链被配置为选择性地提供关于输入时钟信号的精细延迟调整。微步延迟链还包括多个并行信号路径，其中一个或多个并行信号路径被电容性加载以提供精细延迟调整。

17. 发明授权

US06967861B2 Method and apparatus for improving cycle time in a quad data rate SRAM device 有权
标题翻译：用于改善四倍数据速率SRAM器件中的周期时间的方法和装置
公开(公告)号：US06967861B2
公开(公告)日：2005-11-22
申请号：US10708379
申请日：2004-02-27
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
IPC分类号： G11C8/00 , G11C11/00 , G11C11/413
CPC分类号： G11C11/413
摘要： A method for implementing a self-timed, read to write operation in a memory storage device. In an exemplary embodiment, the method includes capturing a read address during a first half of a current clock cycle, and commencing a read operation so as to read data corresponding to the captured read address onto a pair of bit lines. A write operation is commenced for the current clock cycle so as to cause write data to appear on the pair of bit lines as soon as the read data from the captured read address is amplified by a sense amplifier, wherein the write operation uses a previous write address captured during a preceding clock cycle. A current write address is captured during a second half of the current clock cycle, said current write address used for a write operation implemented during a subsequent clock cycle, wherein the write operation for the current clock cycle is timed independent of the current write address captured during said second half of the current clock cycle.
摘要翻译：一种用于在存储器存储设备中实现自定时的读写操作的方法。在一个示例性实施例中，该方法包括在当前时钟周期的前半部分期间捕获读取地址，并开始读取操作，以便将对应于所捕获的读取地址的数据读取到一对位线上。一旦当前时钟周期开始写入操作，以便一旦来自捕获的读取地址的读取数据被读出放大器放大，就会使写入数据出现在该对位线上，其中写入操作使用先前的写入在前一个时钟周期捕获的地址。在当前时钟周期的后半段期间捕获当前写入地址，所述当前写入地址用于在随后的时钟周期期间实现的写入操作，其中当前时钟周期的写入操作被独立于捕获的当前写入地址在当前时钟周期的后半段。

18. 发明申请

US20050184775A1 SYSTEM AND METHOD FOR IMPLEMENTING A MICRO-STEPPING DELAY CHAIN FOR A DELAY LOCKED LOOP 失效
公开(公告)号：US20050184775A1
公开(公告)日：2005-08-25
申请号：US10708287
申请日：2004-02-23
申请人： Harold Pilo , Reid Wistort
发明人： Harold Pilo , Reid Wistort
IPC分类号： H03K5/00 , H03K5/13 , H03L7/06 , H03L7/081
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03K2005/00221 , H03L7/0818
摘要： A delay locked loop for use in an integrated circuit device includes a coarse delay chain in series with a micro-stepped delay chain. The coarse delay chain includes a plurality of coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and the micro-stepped delay chain is configured for selectively providing a fine delay adjustment with respect to the input clock signal. The micro-stepped delay chain further includes a plurality of parallel signal paths, wherein one or more of the parallel signal paths are capacitively loaded so as to provide the fine delay adjustment.

19. 发明授权

US06922076B2 Scalable termination 失效
标题翻译：可扩展终止
公开(公告)号：US06922076B2
公开(公告)日：2005-07-26
申请号：US10604936
申请日：2003-08-27
申请人： George M. Braceras , Reid C. Hutchins , Harold Pilo
发明人： George M. Braceras , Reid C. Hutchins , Harold Pilo
IPC分类号： H04L25/02 , H03K17/16
CPC分类号： H04L25/0298 , H04L25/0278
摘要： In a first aspect, a first method is provided for providing multiple termination values using a plurality of binary termination signals. The first method includes the steps of (1) determining a characteristic impedance of a first port by generating a plurality of binary termination signals; and (2) modifying a characteristic impedance of a second port by manipulating one or more of the plurality of binary termination signals. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种使用多个二进制终止信号来提供多个终止值的第一方法。第一种方法包括以下步骤：（1）通过产生多个二进制终止信号来确定第一端口的特性阻抗; 和（2）通过操纵多个二进制终止信号中的一个或多个来修改第二端口的特性阻抗。提供了许多其他方面。

20. 发明授权

US06897674B2 Adaptive integrated circuit based on transistor current measurements 有权
标题翻译：基于晶体管电流测量的自适应集成电路
公开(公告)号：US06897674B2
公开(公告)日：2005-05-24
申请号：US10604186
申请日：2003-06-30
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
IPC分类号： G01R31/30 , G01R31/26
CPC分类号： G01R31/3004
摘要： A method of tuning an integrated circuit on an integrated circuit chip including: performing a drain current at saturation measurement of one or more test field effect transistors on the integrated circuit chip; selectively programming fuses of a bank of fuses on the integrated circuit chip based on the drain current at saturation measurement; and tuning an output of the integrated circuit based on a pattern of blown and un-blown fuses in the bank of fuses.
摘要翻译：一种对集成电路芯片上的集成电路进行调谐的方法，包括：在集成电路芯片上的一个或多个测试场效应晶体管的饱和测量时执行漏极电流; 基于饱和度测量时的漏极电流有选择地对集成电路芯片上的熔丝组进行熔丝; 并根据保险丝库中的熔断和未熔断保险丝的模式调整集成电路的输出。

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