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11. 发明授权

US5903195A Automatically ranging phase locked loop circuit for microprocessor clock generation 失效
标题翻译：自动测距锁相环电路，用于微处理器时钟产生
公开(公告)号：US5903195A
公开(公告)日：1999-05-11
申请号：US16848
申请日：1998-01-30
申请人： Eric John Lukes , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , James David Strom , Dana Marie Woeste
IPC分类号： H03L7/095 , H03L7/099 , H03L7/10 , H03L7/12
CPC分类号： H03L7/095 , H03L7/0995 , H03L7/10 , Y10S331/02
摘要： An improved phase locked loop (PLL) circuit is provided for use in microprocessor clock generation. A ring oscillator provides an output frequency signal. A voltage to current converter converts differential control voltages to a variable reference current applied to the ring oscillator. A range control reference current generator applies a range control reference current to the ring oscillator. A range control operatively controls the range control reference current generator to sequentially change the range control reference current applied to the ring oscillator. A lock detector coupled to the range control compares the output frequency signal and a reference frequency signal and responsive to the compares signals applies a locked signal to the range control. Responsive to an applied locked signal, the range control stops changing ranges. The phase locked loop (PLL) circuit automatically sweeps through multiple frequency subranges responsive to the range control. A control signal is applied to the voltage to current converter for selectively controlling an operational mode of the voltage to current converter from a squelched operational mode to an unsquelched operational mode after a set time period. This control signal also is applied to the range control, so that the range control stops changing ranges.
摘要翻译：提供改进的锁相环（PLL）电路用于微处理器时钟产生。环形振荡器提供输出频率信号。电压 - 电流转换器将差分控制电压转换为施加到环形振荡器的可变参考电流。范围控制参考电流发生器将范围控制参考电流施加到环形振荡器。范围控制可操作地控制距离控制参考电流发生器以顺序地改变施加到环形振荡器的范围控制参考电流。耦合到量程控制的锁定检测器比较输出频率信号和参考频率信号，并且响应于比较信号将锁定信号施加到范围控制。响应于所施加的锁定信号，范围控制停止变化范围。锁相环（PLL）电路根据范围控制自动扫描多个频率子范围。控制信号被施加到电压到电流转换器，用于在设定的时间段之后选择性地将电压/电流转换器的操作模式从压缩操作模式控制到未校准的操作模式。该控制信号也适用于量程控制，使范围控制停止变化范围。

12. 发明授权

US07453293B2 High frequency divider state correction circuit 失效
标题翻译：高分频器状态校正电路
公开(公告)号：US07453293B2
公开(公告)日：2008-11-18
申请号：US11467972
申请日：2006-08-29
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
摘要翻译：本发明提供一种自校正状态电路。第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。第一校正电路耦合到第二触发器并且被配置为产生校正输出。第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

13. 发明授权

US07119587B2 High frequency divider state correction circuit 失效
标题翻译：高分频器状态校正电路
公开(公告)号：US07119587B2
公开(公告)日：2006-10-10
申请号：US10850400
申请日：2004-05-20
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted to a third flip flop. In one aspect, the received value transmitted to the third flip flop comprises an unaltered received value. In another aspect, the received value transmitted to the third flip flop comprises transmitting an altered received value. This allows for an incorrect state within the state machine to change to a correct state after a few clock pulses.
摘要翻译：本发明提供了状态校正。从触发器接收状态电路中的第一值。接收到的值被发送到第二触发器。如果出现错误状况，则第二触发器内的接收值被改变。接收到的值被发送到第三个触发器。一方面，发送到第三触发器的接收值包括未改变的接收值。在另一方面，发送到第三触发器的接收值包括发送改变的接收值。这允许状态机中的错误状态在几个时钟脉冲之后变为正确的状态。

14. 发明授权

US06218901B1 High speed differential output driver with increased voltage swing and predrive common mode adjustment 有权
标题翻译：高速差分输出驱动器，具有增加的电压摆幅和预调制共模调整
公开(公告)号：US06218901B1
公开(公告)日：2001-04-17
申请号：US09415675
申请日：1999-10-12
申请人： Eric John Lukes , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , James David Strom , Dana Marie Woeste
IPC分类号： H03F345
CPC分类号： H03F3/45179 , H03F3/3028 , H03F3/45085 , H03F3/45937 , H03F3/505 , H03F3/68 , H03F2203/45476 , H03F2203/45612 , H03F2203/45648 , H03F2203/45696 , H03K19/017563 , H03K19/018528
摘要： A high speed differential output driver is provided with increased voltage swing and predrive common mode adjustment. The high speed differential output driver includes a differential input with a voltage amplifier receiving the differential input signal and a common mode adjustment signal and providing an adjustable voltage amplified signal. An emitter follower is coupled to the voltage amplifier. The emitter follower provides a level shifted voltage amplified signal. A driver is coupled to the emitter follower receiving the level shifted voltage amplified signal and providing a driver output signal.
摘要翻译：提供高速差分输出驱动器，具有增加的电压摆幅和预调制共模调整。高速差分输出驱动器包括具有接收差分输入信号的电压放大器和共模调整信号的差分输入，并提供可调电压放大信号。射极跟随器耦合到电压放大器。射极跟随器提供电平移位电压放大信号。驱动器耦合到接收电平移位电压放大信号的发射极跟随器，并提供驱动器输出信号。

15. 发明授权

US6060939A Digitally controlled differential delay line circuit and method of controlling same 失效
标题翻译：数字控制差动延迟线电路及其控制方法
公开(公告)号：US6060939A
公开(公告)日：2000-05-09
申请号：US176140
申请日：1998-10-21
申请人： Dana Marie Woeste , James David Strom
发明人： Dana Marie Woeste , James David Strom
IPC分类号： H03H11/26 , H03K17/62
CPC分类号： H03H11/265
摘要： An apparatus and method for delaying a signal using a variable delay line circuit. A variable delay line circuit includes first and second delay lines, each including a plurality of delay elements. A multiplexer is coupled to respective outputs of the first and second delay lines and selectively couples the output of one of the first or second delay lines to an output of the multiplexer. A control circuit is coupled to the multiplexer and the first and second delay lines, and controls the multiplexer so as to produce a delayed signal at the multiplexer output using one of the first or second delay lines, and changes a delay factor of the other one of the first or second delay lines by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines. A reference voltage source is coupled to each of the delay elements and provides a reference voltage maintained at a substantially constant amplitude with respect to the power supply to each of the delay elements. The delayed signal may be a differential signal. Each of the delay elements may include one or more adjustable loads or adjustable current sources. An adjustable load may be implemented using P-FETs. In one embodiment, at least one of the delay elements of the first and second delay lines includes a plurality of selectable delay devices, each of which is associated with one of a plurality of selectable delay factors.
摘要翻译：一种使用可变延迟线电路来延迟信号的装置和方法。可变延迟线电路包括第一和第二延迟线，每条延迟线包括多个延迟元件。多路复用器耦合到第一和第二延迟线的相应输出，并且选择性地将第一或第二延迟线之一的输出耦合到多路复用器的输出。控制电路耦合到多路复用器和第一和第二延迟线，并且控制多路复用器，以便使用第一或第二延迟线之一在多路复用器输出端产生延迟信号，并改变另一个延迟系数的延迟因子通过改变第一或第二延迟线中的另一个的一个或多个延迟元件的电阻和电流来控制第一或第二延迟线。参考电压源耦合到每个延迟元件，并提供相对于每个延迟元件的电源维持在基本上恒定幅度的参考电压。延迟信号可以是差分信号。每个延迟元件可以包括一个或多个可调负载或可调电流源。可以使用P-FET实现可调负载。在一个实施例中，第一和第二延迟线的延迟元件中的至少一个包括多个可选择的延迟装置，每个延迟装置与多个可选择的延迟因子之一相关联。

16. 发明授权

US5726592A Self biased low-voltage differential signal detector 失效
标题翻译：自偏置低压差分信号检测器
公开(公告)号：US5726592A
公开(公告)日：1998-03-10
申请号：US572886
申请日：1995-12-18
申请人： Donald Joseph Schulte , James David Strom
发明人： Donald Joseph Schulte , James David Strom
IPC分类号： H03F3/45 , H03K5/24 , H03K5/22
CPC分类号： H03F3/45076 , H03K5/2481
摘要： A low voltage differential signal detector capable of detecting low-voltage differential signals over a large common-mode voltage range. The signal detector uses two differential pairs of opposite conductivity type, coupled to each other in a self-biasing manner to detect low voltage swings in a signal over a large common-mode voltage range. Depending upon the common-mode voltage level of the signal, the low-voltage level swings will be detected by one of the differential pairs, the other of the differential pairs or both.
摘要翻译：一种低压差分信号检测器，能够在大的共模电压范围内检测低电压差分信号。信号检测器使用两个相反导电类型的差分对，以自偏置方式彼此耦合，以检测大共模电压范围内的信号中的低电压摆幅。根据信号的共模电压电平，低电压电平摆幅将由差分对之一，差分对中的另一个或两者互相检测。

17. 发明授权

US06342793B1 Method and system for sending large numbers of CMOS control signals into a separate quiet analog power domain 失效
标题翻译：将大量CMOS控制信号发送到单独的静音模拟电源域的方法和系统
公开(公告)号：US06342793B1
公开(公告)日：2002-01-29
申请号：US09433394
申请日：1999-11-03
申请人： Eric John Lukes , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , James David Strom , Dana Marie Woeste
IPC分类号： H03K190175
CPC分类号： H03K19/00346 , H03K19/017563
摘要： A CMOS signal transmission system for sending a large amount of CMOS signals into a separate quiet analog power domain. Transmission system comprises a converter sub-system which provides at least another device stage through which noise in the CMOS signals must flow and be attenuated to provide converted CMOS signals and a multiplexer coupled to the converter wherein the multiplexer receives converted CMOS signals from the converter sub-system and also receives delayed path control signals. The converter comprises a constant current source for providing a high level voltage reference and a constant current, two complimentary pass gates, and two sets of components for providing paths to ground from the constant current source through the two complimentary pass gates. When CMOS input signal is high and Complimentary CMOS input signal is low, the pass gate comprising transistors T9 and T1 is on and transistors T8 and T0 are off and connection BSEL is pulled high turning on bipolar transistor Q9 allowing current to flow through Q9 and pulling net SB low and selecting inputs B0, B1 to be transferred to ECL Differential Outputs. Likewise, when CMOS input signal is low and Complimentary CMOS input signal is high, pass gate comprising transistors T8 and T0 is on, and transistors T9 and T1 are off, and connection ASEL is pulled high turning on bipolar transistor Q8 allowing current to flow through Q8 and pulling net SA low and selecting inputs A0, A1 to be transferred to ECL Differential Outputs.
摘要翻译： CMOS信号传输系统，用于将大量的CMOS信号发送到独立的静态模拟电源域。传输系统包括转换器子系统，其提供至少另一个器件级，CMOS信号中的噪声必须通过该器件级流动并被衰减以提供转换的CMOS信号;以及耦合到转换器的多路复用器，其中多路复用器从转换器子接收转换的CMOS信号并且还接收延迟路径控制信号。该转换器包括用于提供高电平电压基准的恒流源和恒定电流两个互补栅极，以及用于通过两个互补栅极从恒定电流源提供到地的路径的两组元件。当CMOS输入信号为高电平且免费CMOS输入信号为低电平时，包括晶体管T9和T1的通过栅导通，晶体管T8和T0断开，并连接BSEL被拉高，双极晶体管Q9导通，允许电流流过Q9并拉动净SB低，并选择输入B0，B1传输到ECL差分输出。同样地，当CMOS输入信号为低电平，并且免费CMOS输入信号为高电平时，包括晶体管T8和T0的通路导通，晶体管T9和T1截止，并且连接ASEL被拉高，导通双极晶体管Q8，允许电流流过 Q8和拉低SA SA，并选择输入A0，A1传输到ECL差分输出。

18. 发明授权

US06232806B1 Multiple-mode clock distribution apparatus and method with adaptive skew compensation 失效
标题翻译：具有自适应偏移补偿的多模式时钟分配装置和方法
公开(公告)号：US06232806B1
公开(公告)日：2001-05-15
申请号：US09177142
申请日：1998-10-21
申请人： Dana Marie Woeste , James David Strom , Bruce George Rudolph
发明人： Dana Marie Woeste , James David Strom , Bruce George Rudolph
IPC分类号： H03K706
CPC分类号： G06F1/10 , H03K5/133 , H03L7/07 , H03L7/0814
摘要： An apparatus and method for distributing a clock signal within circuitry disposed on a number of separate system cards includes a first system card that generates a reference clock signal representative of a fixed delay of a system clock signal. A number of variable clock signals are produced using the system clock signal. Each of a number of system cards separate from the first system card receive one of the variable clock signals. A delay associated with the reference clock signal is typically longer than a delay associated with each of the variable clock signals. The phase of each of the variable clock signals is adjusted to a substantially in-phase relationship with respect to the reference clock signal in response to a phase difference between the reference clock signal an output signal received from each of the separate system cards. Producing each of the variable clock signals may involve selecting between a first delay line and a second delay line, and then producing the variable delay signal using the selected first or second delay line. A delay factor of the non-selected first or second delay line may be changed by varying a resistance and a current of one or more delay elements of the non-selected first or second delay lines. The circuitry is selectably operable in a slave or buffer-type clock repowering mode or an adaptive mode. The variable clock signals and the output signals may respectively comprise low voltage differential signals (LVDS) or CMOS level signals.
摘要翻译：一种用于在设置在多个单独的系统卡上的电路内分配时钟信号的装置和方法包括产生表示系统时钟信号的固定延迟的参考时钟信号的第一系统卡。使用系统时钟信号产生多个可变时钟信号。与第一系统卡分开的多个系统卡中的每一个都接收可变时钟信号之一。与参考时钟信号相关联的延迟通常比与每个可变时钟信号相关联的延迟更长。每个可变时钟信号的相位响应于参考时钟信号从每个单独的系统卡接收的输出信号之间的相位差而相对于参考时钟信号被调整到基本上同相的关系。产生每个可变时钟信号可以包括在第一延迟线和第二延迟线之间进行选择，然后使用所选择的第一或第二延迟线产生可变延迟信号。可以通过改变未选择的第一或第二延迟线的一个或多个延迟元件的电阻和电流来改变未选择的第一或第二延迟线的延迟因子。电路可选择地以从属或缓冲型时钟重新供电模式或自适应模式工作。可变时钟信号和输出信号可以分别包括低电压差分信号（LVDS）或CMOS电平信号。

19. 发明授权

US5831484A Differential charge pump for phase locked loop circuits 失效
标题翻译：差分电荷泵用于锁相环电路
公开(公告)号：US5831484A
公开(公告)日：1998-11-03
申请号：US826436
申请日：1997-03-18
申请人： Eric John Lukes , James David Strom
发明人： Eric John Lukes , James David Strom
IPC分类号： H03L7/089
CPC分类号： H03L7/0895 , H03L7/0896
摘要： A differential charge pump is provided for use with phase locked loop (PLL) circuits including a differential loop filter and a common mode bias circuit for maintaining a predetermined bias voltage value on a high voltage filter side of the loop filter. The differential charge pump includes a reference current source. First and second current mirrors are coupled to the reference current source for providing a first mirror current and a second mirror current. A first switching transistor coupled to the first current mirror receives an input UP signal conducts current from a first side of the loop filter. A second switching transistor coupled to the second current mirror receives an input DOWN signal and conducts current from a second side of the loop filter. The first and second current mirror and switching transistors are formed by N-channel metal oxide semiconductor (NMOS) devices. The differential charge pump enables a large differential output voltage with low phase error.
摘要翻译：提供差分电荷泵用于包括差分环路滤波器和共模偏置电路的锁相环（PLL）电路，用于在环路滤波器的高电压滤波器侧上保持预定的偏置电压值。差分电荷泵包括参考电流源。第一和第二电流镜耦合到参考电流源，以提供第一反射镜电流和第二反射镜电流。耦合到第一电流镜的第一开关晶体管接收输入UP信号从环路滤波器的第一侧传导电流。耦合到第二电流镜的第二开关晶体管接收输入的DOWN信号，并且从环路滤波器的第二侧传导电流。第一和第二电流镜和开关晶体管由N沟道金属氧化物半导体（NMOS）器件形成。差分电荷泵能够实现具有低相位误差的大差分输出电压。

20. 发明授权

US5815694A Apparatus and method to change a processor clock frequency 失效
标题翻译：改变处理器时钟频率的装置和方法
公开(公告)号：US5815694A
公开(公告)日：1998-09-29
申请号：US576172
申请日：1995-12-21
申请人： Paul Allen Ganfield , Charles Luther Johnson , James David Strom
发明人： Paul Allen Ganfield , Charles Luther Johnson , James David Strom
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： An apparatus and method for providing a variable frequency clock source is described wherein the frequency may be changed while maintaining the phase of the clock signal. A frequency conversation circuit, such as a phase locked loop (PLL), is employed to change the frequency of the clock and is controlled by a control unit which maintains the phase of the output clock signal while undergoing a frequency change operation.
摘要翻译：描述了一种用于提供可变频率时钟源的装置和方法，其中可以在保持时钟信号的相位的同时改变频率。使用诸如锁相环（PLL）的频率对话电路来改变时钟的频率，并且由控制单元控制，该控制单元在经历频率改变操作时保持输出时钟信号的相位。

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