专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07496776B2 Power throttling method and apparatus 失效
标题翻译：功率节流方法和装置
公开(公告)号：US07496776B2
公开(公告)日：2009-02-24
申请号：US10645024
申请日：2003-08-21
申请人： James Allan Kahle , David J. Shippy , Albert James Van Norstrand, Jr.
发明人： James Allan Kahle , David J. Shippy , Albert James Van Norstrand, Jr.
IPC分类号： G06F1/32
CPC分类号： G06F9/30112 , G06F1/3203 , G06F1/3287 , G06F9/30141 , G06F9/30189 , Y02D10/171 , Y02D50/20
摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.
摘要翻译：公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。还防止时钟信号被施加到这些未使用的组件。作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。

12. 发明授权

US07114035B2 Software-controlled cache set management with software-generated class identifiers 失效
标题翻译：软件控制的缓存集管理与软件生成的类标识符
公开(公告)号：US07114035B2
公开(公告)日：2006-09-26
申请号：US10655365
申请日：2003-09-04
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

13. 发明授权

US07107363B2 Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation 失效
标题翻译：具有用于计算应用的带宽管理的微处理器和管理带宽分配的相关方法
公开(公告)号：US07107363B2
公开(公告)日：2006-09-12
申请号：US10464882
申请日：2003-06-19
申请人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Takeshi Yamazaki
发明人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Takeshi Yamazaki
IPC分类号： G06F3/00
CPC分类号： G06F9/5011 , G06F2209/5014
摘要： The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing element and configured to shape storage requests for the processing of the application. In this embodiment, the microprocessor further includes bandwidth management circuitry coupled to the access shaper and configured to track the bandwidth usage based on the requests. A method of coordinating bandwidth allocation and a processor assembly are also disclosed.
摘要翻译：本发明在一个方面公开了一种微处理器。在一个实施例中，微处理器包括被配置为使用带宽来处理应用的处理元件。微处理器还包括一个接入整形器，它与处理元件相耦合，并配置成形成用于处理应用的存储请求。在该实施例中，微处理器还包括耦合到接入整形器的带宽管理电路，并且被配置为基于请求跟踪带宽使用。还公开了一种协调带宽分配的方法和处理器组件。

14. 发明授权

US07010626B2 DMA prefetch 失效
标题翻译： DMA预取
公开(公告)号：US07010626B2
公开(公告)日：2006-03-07
申请号：US11057454
申请日：2005-02-14
申请人： James Allan Kahle
发明人： James Allan Kahle
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a processor. A load access pattern of the DMA mechanism is detected. At least one potential load of data is predicted based on the load access pattern. In response to the prediction, the data is prefetched from a system memory to a cache before a DMA command requests the data.
摘要翻译：提供了一种用于将数据从系统存储器预取到计算机系统中用于直接存储器访问（DMA）机制的高速缓存的方法和装置。为处理器设置了DMA机制。检测到DMA机制的负载访问模式。基于负载访问模式预测至少一个潜在的数据负载。响应于该预测，在DMA命令请求数据之前，将数据从系统存储器预取到高速缓存。

15. 发明授权

US06779049B2 Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism 有权
标题翻译：具有附加处理单元的对称多处理系统能够访问共享存储器而不在结构上配置地址转换机制
公开(公告)号：US06779049B2
公开(公告)日：2004-08-17
申请号：US09736585
申请日：2000-12-14
申请人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman , Masakazu Suzuoki , Takeshi Yamazaki
发明人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman , Masakazu Suzuoki , Takeshi Yamazaki
IPC分类号： G06F1328
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

16. 发明授权

US06697939B1 Basic block cache microprocessor with instruction history information 失效
标题翻译：具有指令历史信息的基本块缓存微处理器
公开(公告)号：US06697939B1
公开(公告)日：2004-02-24
申请号：US09477569
申请日：2000-01-06
申请人： James Allan Kahle
发明人： James Allan Kahle
IPC分类号： G06F900
CPC分类号： G06F9/3814 , G06F9/30174 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3861
摘要： A processor, data processing system, and a related method of execution are disclosed. The processor is suitable for receiving a set of instructions and organizing the set of instructions into an instruction group. The instruction group is then dispatched for execution. Upon executing the instruction group, instruction history information indicative of an exception event associated with the instruction group is recorded. Thereafter, the execution of the instruction is modified responsive to the instruction history information to prevent the exception event from occurring during a subsequent execution of the instruction group. The processor includes a storage facility such as an instruction cache, an L2 cache or a system memory, a cracking unit, and a basic block cache. The cracking unit is configured to receive a set of instructions from the storage facility. The cracking unit is adapted to organize the set of instructions into an instruction group.
摘要翻译：公开了一种处理器，数据处理系统和相关的执行方法。处理器适用于接收一组指令，并将该组指令组织到指令组中。然后调度指令组以执行。在执行指令组时，记录指示与指令组相关联的异常事件的指令历史信息。此后，响应于指令历史信息修改指令的执行，以防止在指令组的后续执行期间发生异常事件。处理器包括诸如指令高速缓存，L2高速缓存或系统存储器，破解单元和基本块高速缓存之类的存储设备。破裂单元被配置为从存储设施接收一组指令。裂解单元适于将该组指令组织成指令组。

17. 发明授权

US06662360B1 Method and system for software control of hardware branch prediction mechanism in a data processor 失效
标题翻译：数据处理器中硬件分支预测机制的软件控制方法与系统
公开(公告)号：US06662360B1
公开(公告)日：2003-12-09
申请号：US09407105
申请日：1999-09-27
申请人： Robert William Hay , James Allan Kahle , Brian R. Konigsburg , David Stephen Levitan , Balaram Sinharoy
发明人： Robert William Hay , James Allan Kahle , Brian R. Konigsburg , David Stephen Levitan , Balaram Sinharoy
IPC分类号： G06F944
CPC分类号： G06F9/3846 , G06F9/3848
摘要： A method and system is disclosed for software manipulation of hardware prediction mechanism in a data processor with software prediction. The hardware branch prediction mechanism is enhanced with at least two bits for path prediction. These bits are settable by a software and are capable of overriding the hardware branch prediction mechanism. Branch prediction information is encoded into a branch instruction in the software. This information includes a pre-determined value for each bit. Finally, a branch path of said instruction is predicted based on the value of the bits.
摘要翻译：公开了一种用于软件预测的数据处理器中硬件预测机制的软件操纵的方法和系统。用于路径预测的至少两个比特来增强硬件分支预测机制。这些位可由软件设置，并能够覆盖硬件分支预测机制。分支预测信息被编码成软件中的分支指令。该信息包括每个位的预定值。最后，基于比特的值来预测所述指令的分支路径。

18. 发明授权

US06629233B1 Secondary reorder buffer microprocessor 有权
标题翻译：二次重排缓冲微处理器
公开(公告)号：US06629233B1
公开(公告)日：2003-09-30
申请号：US09506527
申请日：2000-02-17
申请人： James Allan Kahle
发明人： James Allan Kahle
IPC分类号： G06F930
CPC分类号： G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method, processor, and data processing system for enabling maximum instruction issue despite the presence of complex instructions that require multiple rename registers is disclosed. The method includes allocating a first rename register from a first reorder buffer for storing the contents of a first register affected by the complex instruction. A second rename register from a second reorder buffer is then allocated for storing the contents of a second register affected by the complex instruction. In an embodiment in which the first reorder buffer supports a maximum number of allocations per cycle, the allocation of the second register using the second reorder buffer prevents the complex instruction from requiring multiple allocation slots in the first reorder buffer. The method may further include issuing a second instruction that contains a dependency on a register that is allocated in the secondary reorder buffer. In one embodiment, reorder buffer information indicating the second instruction's dependence on a register allocated in the secondary reorder buffer is associated with the second instruction such that, when the second instruction is issued subsequently, the reorder buffer information is used to restrict the issue unit to checking only the secondary reorder buffer for dependencies.
摘要翻译：公开了一种方法，处理器和数据处理系统，用于实现最大化指令发布，尽管存在需要多个重命名寄存器的复杂指令。该方法包括从第一重排序缓冲器分配第一重命名寄存器，用于存储受复合指令影响的第一寄存器的内容。然后分配来自第二重排序缓冲器的第二重命名寄存器用于存储受复合指令影响的第二寄存器的内容。在其中第一重排序缓冲器支持每个周期的最大分配数量的实施例中，使用第二重排序缓冲器分配第二寄存器防止复指令在第一重排序缓冲器中需要多个分配时隙。该方法还可以包括发出包含对在二次重排序缓冲器中分配的寄存器的依赖性的第二指令。在一个实施例中，指示第二指令对在二次重排序缓冲器中分配的寄存器的依赖性的重新排序缓冲器信息与第二指令相关联，使得当随后发出第二指令时，重排序缓冲器信息用于将发布单元限制为仅检查辅助重新排序缓冲区以获取依赖关系。

19. 发明授权

US06539500B1 System and method for tracing 失效
标题翻译：系统和追踪方法
公开(公告)号：US06539500B1
公开(公告)日：2003-03-25
申请号：US09428410
申请日：1999-10-28
申请人： James Allan Kahle , Alexander Erik Mericas , Kevin Franklin Reick , Joel M. Tendler
发明人： James Allan Kahle , Alexander Erik Mericas , Kevin Franklin Reick , Joel M. Tendler
IPC分类号： G06F1100
CPC分类号： G06F11/3636
摘要： The present invention discloses a system and method for implementing instruction tracing in a computer system and in particular a computer system with a tightly coupled shared processor central processor unit (CPU). Each of the processors are generally purpose processors that have been modified by design to allow an instruction to execute and simultaneously to be stored and forwarded to shared memory operable as a trace buffer. Since each processor is general purpose, the trace routine necessary for tracing, can by one of the routines or programs that can be written and executed on either of the processors. One of the processors can run, collect and analyze the executed and store instructions of the other processor. Since the processors can be on a single chip the shared memory bus that writes and reads the executed instructions can operate at high speed. Also since the trace function is part of the multiprocessor architecture its speed of operation will scale with the speed of the processors without modification.
摘要翻译：本发明公开了一种用于在计算机系统中实现指令跟踪的系统和方法，特别是具有紧耦合的共享处理器中央处理器单元（CPU）的计算机系统。每个处理器通常是通过设计修改的目的处理器，以允许指令执行并同时被存储并转发到可用作跟踪缓冲器的共享存储器。由于每个处理器是通用目的，因此可以通过其中一个可以在任一处理器上编写和执行的程序之一进行跟踪所需的跟踪例程。其中一个处理器可以运行，收集和分析其他处理器的执行和存储指令。由于处理器可以在单个芯片上，写入和读取执行的指令的共享存储器总线可以高速运行。此外，由于跟踪功能是多处理器架构的一部分，因此操作速度将随着处理器的速度而不变化。

20. 发明授权

US5758140A Method and system for emulating instructions by performing an operation directly using special-purpose register contents 失效
标题翻译：通过直接使用专用寄存器内容进行操作来仿真指令的方法和系统
公开(公告)号：US5758140A
公开(公告)日：1998-05-26
申请号：US581793
申请日：1996-01-25
申请人： James Allan Kahle , Soummya Mallick
发明人： James Allan Kahle , Soummya Mallick
IPC分类号： G06F9/30 , G06F9/318 , G06F9/455 , G06F9/42
CPC分类号： G06F9/30167 , G06F9/30174
摘要： A system and method for improving the performance of a processor that emulates a guest instruction where the guest instruction includes a first and second operand. The first operand is stored in a general purpose register, and the second operand is stored in a special-purpose register. The method and system provides a host instruction that performs an operation using the first operand and the second operand without moving the second operand from the special-purpose register into the general purpose register. This reduces the number of instructions in the semantic routines necessary to operate on immediate data from guest instructions and increases emulation performance.
摘要翻译：一种用于提高仿真访客指令的处理器的性能的系统和方法，其中所述访客指令包括第一和第二操作数。第一个操作数存储在通用寄存器中，第二个操作数存储在专用寄存器中。该方法和系统提供主机指令，其使用第一操作数和第二操作数执行操作，而不将第二操作数从专用寄存器移动到通用寄存器中。这减少了从客户指令对即时数据进行操作所需的语义程序中的指令数量，并增加了仿真性能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式