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11. 发明授权

US06916594B2 Overcoating composition for photoresist and method for forming photoresist pattern using the same 失效
标题翻译：用于光致抗蚀剂的复涂组合物和使用其形成光致抗蚀剂图案的方法
公开(公告)号：US06916594B2
公开(公告)日：2005-07-12
申请号：US10722815
申请日：2003-11-26
申请人： Cheol Kyu Bok , Jae Chang Jung , Seung Chan Moon , Ki Soo Shin
发明人： Cheol Kyu Bok , Jae Chang Jung , Seung Chan Moon , Ki Soo Shin
IPC分类号： G03F7/039 , G03F7/40 , H01L21/027 , G03C1/492
CPC分类号： G03F7/40 , G03F7/0395
摘要： Overcoating compositions for photoresist and methods for reducing linewidth of the photoresist patterns are disclosed. More specifically, an overcoating composition containing acids is coated on a whole surface of a photoresist pattern formed by a common lithography process to diffuse the acids into the photoresist pattern. The photoresist in the portion where the acids are diffused is developed with an alkali solution to be removed. As a result, the linewidth of positive photoresist patterns can be reduced, and the linewidth of negative photoresist patterns can be prevented from slimming in a subsequent linewidth measurement process using SEM.
摘要翻译：公开了用于光致抗蚀剂的覆盖组合物和用于降低光致抗蚀剂图案的线宽的方法。更具体地说，在通过普通光刻工艺形成的光致抗蚀剂图案的整个表面上涂覆含有酸的外涂层组合物，以将酸扩散到光刻胶图案中。酸分散的部分中的光致抗蚀剂用待除去的碱溶液显影。结果，可以减少正光致抗蚀剂图案的线宽，并且可以在使用SEM的随后的线宽测量过程中防止负光致抗蚀剂图案的线宽减轻。

12. 发明申请

US20080272467A1 Method for Forming Fine Pattern of Semiconductor Device 失效
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：US20080272467A1
公开(公告)日：2008-11-06
申请号：US11964988
申请日：2007-12-27
申请人： Cheol Kyu Bok , Keun Do Ban
发明人： Cheol Kyu Bok , Keun Do Ban
IPC分类号： H01L21/306 , H01L29/06
CPC分类号： H01L21/0337 , H01L21/0338 , Y10S438/952
摘要： A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask film to form a deposition pattern, and forming an amorphous carbon pattern at sidewalls of the deposition pattern. The method further includes filling a spin-on-carbon layer over the deposition pattern and the amorphous carbon pattern, polishing the spin-on-carbon layer, the amorphous carbon pattern, and the photoresist pattern to expose the third mask pattern, and performing an etching process to expose the first mask film with the amorphous carbon pattern as an etching mask. The etching process removes the third mask pattern and the exposed second mask pattern. The method also includes removing the spin-on-carbon layer and the amorphous carbon pattern, and forming a first mask pattern with the second mask pattern as an etching mask.
摘要翻译：用于形成半导体器件的精细图案的方法包括在具有下层的衬底上形成沉积膜。沉积膜包括第一，第二和第三掩模膜。该方法还包括在第三掩模膜上形成光致抗蚀剂图案，图案化第三掩模膜以形成沉积图案，并在沉积图案的侧壁处形成无定形碳图案。该方法还包括在沉积图案和无定形碳图案上填充旋涂碳层，研磨自旋碳层，无定形碳图案和光致抗蚀剂图案以暴露第三掩模图案，并执行蚀刻工艺以将无定形碳图案的第一掩模膜暴露为蚀刻掩模。蚀刻工艺去除第三掩模图案和暴露的第二掩模图案。该方法还包括除去碳 - 碳层和无定形碳图案，并且用第二掩模图案形成第一掩模图案作为蚀刻掩模。

13. 发明申请

US20100248153A1 METHOD FOR FORMING PATTERN OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件图案的方法
公开(公告)号：US20100248153A1
公开(公告)日：2010-09-30
申请号：US12473242
申请日：2009-05-27
申请人： Ki Lyoung Lee , Cheol Kyu Bok , Keun Do Ban
发明人： Ki Lyoung Lee , Cheol Kyu Bok , Keun Do Ban
IPC分类号： G03F7/20
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method for forming a pattern of a semiconductor device is provided. Specifically, in a method for manufacturing a NAND flash memory device using a spacer patterning process, a dummy pattern, which is not used in an actual device operation, is additionally formed in a peripheral circuit region when a photoresist pattern for forming a string pattern is formed in a cell region. As a result, the edge photoresist pattern is prevented from being bent, and a critical dimension difference between the center region and the edge region of the photoresist pattern lo is not generated, thereby improving a margin of DOF to obtain a reliable semiconductor device.
摘要翻译：提供了形成半导体器件的图案的方法。具体地，在使用间隔物图案化工艺的NAND闪速存储器件的制造方法中，当用于形成线图案的光致抗蚀剂图案是（...）形状时，在外围电路区域中另外形成不用于实际器件操作的虚拟图案形成在细胞区域中。结果，防止边缘光致抗蚀剂图案弯曲，并且不产生光致抗蚀剂图案lo的中心区域和边缘区域之间的临界尺寸差异，从而提高DOF的余量以获得可靠的半导体器件。

14. 发明授权

US07776747B2 Semiconductor device and method for forming pattern in the same 失效
标题翻译：用于在其中形成图案的半导体器件和方法
公开(公告)号：US07776747B2
公开(公告)日：2010-08-17
申请号：US11759055
申请日：2007-06-06
申请人： Keun Do Ban , Cheol Kyu Bok , Jun Hyeub Sun
发明人： Keun Do Ban , Cheol Kyu Bok , Jun Hyeub Sun
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate, forming a second hard mask layer pattern over the first hard mask layer, forming a spacer on a sidewall of the second hard mask layer pattern, selectively etching the first hard mask layer by using the spacer and the second hard mask layer pattern as an etching mask to form a first hard mask layer pattern, forming a first insulating film filling the second hard mask layer pattern and the first hard mask layer pattern, selectively etching the second hard mask layer pattern and the underlying first hard mask layer pattern to form a third hard mask layer pattern, removing the first insulating film and the spacer, and patterning the semiconductor substrate by using the third hard mask layer pattern as an etching mask to form a fine pattern.
摘要翻译：一种用于形成半导体器件的精细图案的方法包括在半导体衬底上形成第一硬掩模层，在第一硬掩模层上形成第二硬掩模层图案，在第二硬掩模层图案的侧壁上形成间隔物通过使用间隔物和第二硬掩模层图案作为蚀刻掩模选择性蚀刻第一硬掩模层以形成第一硬掩模层图案，形成填充第二硬掩模层图案的第一绝缘膜和第一硬掩模层选择性蚀刻第二硬掩模层图案和下面的第一硬掩模层图案以形成第三硬掩模层图案，去除第一绝缘膜和间隔物，并且通过使用第三硬掩模层图案将半导体基板图案化为蚀刻掩模以形成精细图案。

15. 发明授权

US07615497B2 Forming fine pattern of semiconductor device using three mask layers and CMP of spin-on carbon layer 失效
标题翻译：使用三个掩模层和旋涂碳层的CMP形成半导体器件的精细图案
公开(公告)号：US07615497B2
公开(公告)日：2009-11-10
申请号：US11964988
申请日：2007-12-27
申请人： Cheol Kyu Bok , Keun Do Ban
发明人： Cheol Kyu Bok , Keun Do Ban
IPC分类号： H01L21/306 , H01L29/06
CPC分类号： H01L21/0337 , H01L21/0338 , Y10S438/952
摘要： A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask film to form a deposition pattern, and forming an amorphous carbon pattern at sidewalls of the deposition pattern. The method further includes filling a spin-on-carbon layer over the deposition pattern and the amorphous carbon pattern, polishing the spin-on-carbon layer, the amorphous carbon pattern, and the photoresist pattern to expose the third mask pattern, and performing an etching process to expose the first mask film with the amorphous carbon pattern as an etching mask. The etching process removes the third mask pattern and the exposed second mask pattern. The method also includes removing the spin-on-carbon layer and the amorphous carbon pattern, and forming a first mask pattern with the second mask pattern as an etching mask.
摘要翻译：用于形成半导体器件的精细图案的方法包括在具有下层的衬底上形成沉积膜。沉积膜包括第一，第二和第三掩模膜。该方法还包括在第三掩模膜上形成光致抗蚀剂图案，图案化第三掩模膜以形成沉积图案，并在沉积图案的侧壁处形成无定形碳图案。该方法还包括在沉积图案和无定形碳图案上填充旋涂碳层，研磨自旋碳层，无定形碳图案和光致抗蚀剂图案以暴露第三掩模图案，并执行蚀刻工艺以将无定形碳图案的第一掩模膜暴露为蚀刻掩模。蚀刻工艺去除第三掩模图案和暴露的第二掩模图案。该方法还包括除去碳 - 碳层和无定形碳图案，并且用第二掩模图案形成第一掩模图案作为蚀刻掩模。

16. 发明授权

US07550384B2 Semiconductor device and method for forming pattern in the same 有权
标题翻译：用于在其中形成图案的半导体器件和方法
公开(公告)号：US07550384B2
公开(公告)日：2009-06-23
申请号：US11760090
申请日：2007-06-08
申请人： Keun Do Ban , Cheol Kyu Bok
发明人： Keun Do Ban , Cheol Kyu Bok
IPC分类号： H01L21/44
CPC分类号： H01L21/0337 , H01L21/02115 , H01L21/0214 , H01L21/02282 , H01L21/02304 , H01L21/0338 , H01L21/3143 , H01L21/3146 , H01L21/3185
摘要： A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate and a second hard mask layer over the first hard mask layer, selectively etching the second hard mask layer and the first hard mask layer by using a line/space mask as an etching mask to form a second hard mask layer pattern and a first hard mask layer pattern, forming an insulating film filling the second hard mask layer pattern and the first hard mask layer pattern, selectively etching the second hard mask layer and its underlying first hard mask layer pattern by using the insulating film as an etching mask to form a fourth hard mask layer pattern overlying a third hard mask layer pattern, removing the insulating film and the fourth hard mask layer pattern, and patterning the semiconductor substrate by using the third hard mask layer pattern as an etching mask, to form a fine pattern.
摘要翻译：一种形成半导体器件的精细图案的方法包括在半导体衬底上形成第一硬掩模层和在第一硬掩模层上形成第二硬掩模层，通过使用第二硬掩模层和第一硬掩模层选择性地蚀刻第二硬掩模层和第一硬掩模层线/空间掩模作为蚀刻掩模以形成第二硬掩模层图案和第一硬掩模层图案，形成填充第二硬掩模层图案和第一硬掩模层图案的绝缘膜，选择性地蚀刻第二硬掩模通过使用绝缘膜作为蚀刻掩模形成覆盖在第三硬掩模层图案上的第四硬掩模层图案，去除绝缘膜和第四硬掩模层图案，以及使半导体图案化的第一硬掩模层图案通过使用第三硬掩模层图案作为蚀刻掩模来形成精细图案。

17. 发明申请

US20080160763A1 Semiconductor Device And Method For Forming Pattern In The Same 失效
标题翻译：半导体器件及其形成方法
公开(公告)号：US20080160763A1
公开(公告)日：2008-07-03
申请号：US11759055
申请日：2007-06-06
申请人： Keun Do Ban , Cheol Kyu Bok , Jun Hyeub Sun
发明人： Keun Do Ban , Cheol Kyu Bok , Jun Hyeub Sun
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate, forming a second hard mask layer pattern over the first hard mask layer, forming a spacer on a sidewall of the second hard mask layer pattern, selectively etching the first hard mask layer by using the spacer and the second hard mask layer pattern as an etching mask to form a first hard mask layer pattern, forming a first insulating film filling the second hard mask layer pattern and the first hard mask layer pattern, selectively etching the second hard mask layer pattern and the underlying first hard mask layer pattern to form a third hard mask layer pattern, removing the first insulating film and the spacer, and patterning the semiconductor substrate by using the third hard mask layer pattern as an etching mask to form a fine pattern.
摘要翻译：一种用于形成半导体器件的精细图案的方法包括在半导体衬底上形成第一硬掩模层，在第一硬掩模层上形成第二硬掩模层图案，在第二硬掩模层图案的侧壁上形成间隔物通过使用间隔物和第二硬掩模层图案作为蚀刻掩模选择性蚀刻第一硬掩模层以形成第一硬掩模层图案，形成填充第二硬掩模层图案的第一绝缘膜和第一硬掩模层选择性地蚀刻第二硬掩模层图案和下面的第一硬掩模层图案以形成第三硬掩模层图案，去除第一绝缘膜和间隔物，并且通过使用第三硬掩模层图案将半导体基板图案化为蚀刻掩模以形成精细图案。

18. 发明申请

US20080160767A1 Semiconductor Device And Method For Forming Pattern In The Same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20080160767A1
公开(公告)日：2008-07-03
申请号：US11760090
申请日：2007-06-08
申请人： Keun Do Ban , Cheol Kyu Bok
发明人： Keun Do Ban , Cheol Kyu Bok
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/02115 , H01L21/0214 , H01L21/02282 , H01L21/02304 , H01L21/0338 , H01L21/3143 , H01L21/3146 , H01L21/3185
摘要： A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate and a second hard mask layer over the first hard mask layer, selectively etching the second hard mask layer and the first hard mask layer by using a line/space mask as an etching mask to form a second hard mask layer pattern and a first hard mask layer pattern, forming an insulating film filling the second hard mask layer pattern and the first hard mask layer pattern, selectively etching the second hard mask layer and its underlying first hard mask layer pattern by using the insulating film as an etching mask to form a fourth hard mask layer pattern overlying a third hard mask layer pattern, removing the insulating film and the fourth hard mask layer pattern, and patterning the semiconductor substrate by using the third hard mask layer pattern as an etching mask, to form a fine pattern.
摘要翻译：一种形成半导体器件的精细图案的方法包括在半导体衬底上形成第一硬掩模层和在第一硬掩模层上形成第二硬掩模层，通过使用第二硬掩模层和第一硬掩模层选择性地蚀刻第二硬掩模层和第一硬掩模层线/空间掩模作为蚀刻掩模以形成第二硬掩模层图案和第一硬掩模层图案，形成填充第二硬掩模层图案和第一硬掩模层图案的绝缘膜，选择性地蚀刻第二硬掩模通过使用绝缘膜作为蚀刻掩模形成覆盖在第三硬掩模层图案上的第四硬掩模层图案，去除绝缘膜和第四硬掩模层图案，以及使半导体图案化的第一硬掩模层图案通过使用第三硬掩模层图案作为蚀刻掩模来形成精细图案。

19. 发明授权

US08202683B2 Method for forming pattern of semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US08202683B2
公开(公告)日：2012-06-19
申请号：US12473242
申请日：2009-05-27
申请人： Ki Lyoung Lee , Cheol Kyu Bok , Keun Do Ban
发明人： Ki Lyoung Lee , Cheol Kyu Bok , Keun Do Ban
IPC分类号： G03F7/26
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method for forming a pattern of a semiconductor device is provided. Specifically, in a method for manufacturing a NAND flash memory device using a spacer patterning process, a dummy pattern, which is not used in an actual device operation, is additionally formed in a peripheral circuit region when a photoresist pattern for forming a string pattern is formed in a cell region. As a result, the edge photoresist pattern is prevented from being bent, and a critical dimension difference between the center region and the edge region of the photoresist pattern is not generated, thereby improving a margin of DOF to obtain a reliable semiconductor device.
摘要翻译：提供了形成半导体器件的图案的方法。具体地，在使用间隔物图案化工艺的NAND闪速存储器件的制造方法中，当用于形成线图案的光致抗蚀剂图案是（...）形状时，在外围电路区域中另外形成不用于实际器件操作的虚拟图案形成在细胞区域中。结果，防止边缘光致抗蚀剂图案弯曲，并且不产生光致抗蚀剂图案的中心区域和边缘区域之间的临界尺寸差异，从而提高DOF的余量以获得可靠的半导体器件。

20. 发明授权

US07576009B2 Method for forming fine pattern of semiconductor device 有权
标题翻译：用于形成半导体器件精细图案的方法
公开(公告)号：US07576009B2
公开(公告)日：2009-08-18
申请号：US11948224
申请日：2007-11-30
申请人： Ki Lyoung Lee , Cheol Kyu Bok , Keun Do Ban
发明人： Ki Lyoung Lee , Cheol Kyu Bok , Keun Do Ban
IPC分类号： H01L21/027
CPC分类号： H01L21/0337 , H01L21/02115 , H01L21/02134 , H01L21/02137 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/0332 , H01L21/0338 , H01L21/3143 , H01L21/3146 , H01L21/31608 , H01L21/3185 , H01L21/32139
摘要： A method for forming a fine pattern of a semiconductor device comprises forming a deposition pattern including first, second, and third mask patterns over a semiconductor substrate having an underlying layer, side-etching the second mask pattern with the third mask pattern as an etching barrier mask, removing the third mask pattern, forming a spin-on-carbon layer that exposes the upper portion of the second mask pattern, performing an etching process to expose the underlying layer with the spin-on-carbon layer as an etching barrier mask, and removing the spin-on-carbon layer.
摘要翻译：一种用于形成半导体器件的精细图案的方法包括在具有下层的半导体衬底上形成包括第一，第二和第三掩模图案的沉积图案，用第三掩模图案侧蚀刻第二掩模图案作为蚀刻阻挡层掩模，去除第三掩模图案，形成曝光第二掩模图案的上部的自旋碳层，执行蚀刻工艺以使作为蚀刻阻挡掩模的自旋 - 碳层曝光下层，并去除碳 - 碳层。

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