专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07465658B2 Oxygen bridge structures and methods to form oxygen bridge structures 有权
标题翻译：氧桥结构和形成氧桥结构的方法
公开(公告)号：US07465658B2
公开(公告)日：2008-12-16
申请号：US11411430
申请日：2006-04-25
申请人： Ivo Raaijmakers , Pekka J. Soininen , Kai-Erik Elers
发明人： Ivo Raaijmakers , Pekka J. Soininen , Kai-Erik Elers
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , C23C16/0272 , H01L21/28562 , H01L21/32051 , H01L21/76856 , H01L21/76879 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method is proposed for improving the adhesion between a diffusion barrier film and a metal film. Both the diffusion barrier film and the metal film can be deposited in either sequence onto a semiconductor substrate. A substrate comprising a first film, which is one of a diffusion barrier film or a metal film, with the first film being exposed at least at part of the surface area of the substrate, is exposed to an oxygen-containing reactant to create a surface termination of about one monolayer of oxygen-containing groups or oxygen atoms on the exposed parts of the first film. Then the second film, which is the other one of a diffusion barrier film and a metal film, is deposited onto the substrate. Furthermore, an oxygen bridge structure is proposed, the structure comprising a diffusion barrier film and a metal film having an interface with the diffusion barrier film, wherein the interface comprises a monolayer of oxygen atoms.
摘要翻译：提出了改善扩散阻挡膜和金属膜之间的粘合性的方法。扩散阻挡膜和金属膜都可以以任一顺序沉积到半导体衬底上。包含第一膜，其是扩散阻挡膜或金属膜之一，其中第一膜至少部分地暴露于基底的表面区域，以暴露于含氧反应物以形成表面在第一膜的暴露部分上终止约一个单层的含氧基团或氧原子。然后将作为扩散阻挡膜和金属膜中的另一个的第二膜沉积在基板上。此外，提出了氧桥结构，其结构包括扩散阻挡膜和与扩散阻挡膜具有界面的金属膜，其中界面包括单层氧原子。

12. 发明申请

US20090068832A1 THIN FILMS 有权
标题翻译：薄膜
公开(公告)号：US20090068832A1
公开(公告)日：2009-03-12
申请号：US12202132
申请日：2008-08-29
申请人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christrian J. Werkhoven
发明人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christrian J. Werkhoven
IPC分类号： H01L21/4763
CPC分类号： C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译：通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。在所示实施例中，在循环过程中引入了不同量的杂质源。因此，即使对于非常薄的层也提供了梯度栅极电介质。薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。类似地，栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。在一些实施例中，提供了额外的种子层或附加的过渡层。

13. 发明授权

US06861334B2 Method of fabricating trench isolation structures for integrated circuits using atomic layer deposition 有权
标题翻译：使用原子层沉积制造集成电路的沟槽隔离结构的方法
公开(公告)号：US06861334B2
公开(公告)日：2005-03-01
申请号：US09887199
申请日：2001-06-21
申请人： Ivo Raaijmakers , Pekka T. Soininen , Ernst H. A. Granneman
发明人： Ivo Raaijmakers , Pekka T. Soininen , Ernst H. A. Granneman
IPC分类号： H01L21/316 , H01L21/762 , H01L21/76
CPC分类号： H01L21/02164 , H01L21/02145 , H01L21/02178 , H01L21/02216 , H01L21/0228 , H01L21/3141 , H01L21/3144 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/76224
摘要： A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no more than about a monolayer of material, capable of completely filling high aspect ratio trenches. Additionally, the trench-fill material composition can be tailored by processes described herein, particularly to match the coefficient of thermal expansion (CTE) to that of the surrounding substrate within which the trench is formed. Mixed phases of mullite and silica have been found to meet the goals of device isolation and matched CTE. The described process includes mixing atomic layer deposition cycles of aluminum oxide and silicon oxide in ratios selected to achieve the desired composition of the isolation material, namely on the order of 30% alumina and 70% silicon oxide by weight.
摘要翻译：通过原子层沉积形成电介质膜，以保形地填充狭窄的深沟槽，用于器件隔离。所示实施方案的方法包括交替地以一系列循环脉冲气相反应物，其中每个循环不超过约单层材料，能够完全填充高纵横比沟槽。此外，沟槽填充材料组合物可以通过本文所述的方法来定制，特别是使热膨胀系数（CTE）与其中形成沟槽的周围基底的热膨胀系数相匹配。已经发现莫来石和二氧化硅的混合相达到器件隔离和匹配CTE的目标。所描述的方法包括以选择的比例混合氧化铝和氧化硅的原子层沉积循环，以达到分离材料的所需组成，即按重量计30％氧化铝和70％氧化硅。

14. 发明授权

US06699783B2 Method for controlling conformality with alternating layer deposition 有权
标题翻译：用交替层沉积控制共形的方法
公开(公告)号：US06699783B2
公开(公告)日：2004-03-02
申请号：US10303355
申请日：2002-11-21
申请人： Ivo Raaijmakers , Pekka T. Soininen , Ernst H. A. Granneman , Suvi P. Haukka
发明人： Ivo Raaijmakers , Pekka T. Soininen , Ernst H. A. Granneman , Suvi P. Haukka
IPC分类号： H01L214763
CPC分类号： C23C16/045 , C23C16/45525 , H01L21/28562 , H01L21/32051 , H01L21/7681 , H01L21/76814 , H01L21/76825 , H01L21/76828 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L21/76856 , H01L21/76864 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.
摘要翻译：提供了用于集成电路中的双镶嵌结构的保形衬里的方法和结构，特别是在多孔材料中形成的开口。沟槽和接触通孔形成在绝缘层中。沟槽和通孔的侧壁上的孔堵塞，然后将结构暴露于交替的化学物质以形成所需衬里材料的单层。在示例性工艺流程中，密封层的化学或物理气相沉积（CVD或PVD）由于不完全的一致性而阻塞孔，并且之后是原子层沉积（ALD），特别是交替脉冲的金属卤化物和注入恒定的氨气载体流。交替的方法也可以布置成在绝缘体的孔内以CVD模式起作用，因为反应物不容易从脉冲之间的孔中吹扫。自身端接的金属层因此与氮气反应。接近完美的台阶覆盖允许扩散阻挡功能的最小厚度，从而使任何给定沟槽和通孔尺寸的后续填充金属的体积最大化。

15. 发明申请

US20110256718A1 THIN FILMS 审中-公开
标题翻译：薄膜
公开(公告)号：US20110256718A1
公开(公告)日：2011-10-20
申请号：US13079562
申请日：2011-04-04
申请人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
发明人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
IPC分类号： H01L21/285
CPC分类号： C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译：通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。在所示实施例中，在循环过程中引入了不同量的杂质源。因此，即使对于非常薄的层也提供了梯度栅极电介质。薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。类似地，栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。在一些实施例中，提供了额外的种子层或附加的过渡层。

16. 发明授权

US07981791B2 Thin films 有权
标题翻译：薄膜
公开(公告)号：US07981791B2
公开(公告)日：2011-07-19
申请号：US12202132
申请日：2008-08-29
申请人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
发明人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey , Christiaan J. Werkhoven
IPC分类号： H01L21/4763
CPC分类号： C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译：通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。在所示实施例中，在循环过程中引入了不同量的杂质源。因此，即使对于非常薄的层也提供了梯度栅极电介质。薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。类似地，栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。在一些实施例中，提供了额外的种子层或附加的过渡层。

17. 发明授权

US07276774B2 Trench isolation structures for integrated circuits 有权
标题翻译：集成电路的沟槽隔离结构
公开(公告)号：US07276774B2
公开(公告)日：2007-10-02
申请号：US10867826
申请日：2004-06-14
申请人： Ivo Raaijmakers , Pekka T. Soininen , Ernst H. A. Granneman
发明人： Ivo Raaijmakers , Pekka T. Soininen , Ernst H. A. Granneman
IPC分类号： H01L21/762
CPC分类号： H01L21/02164 , H01L21/02145 , H01L21/02178 , H01L21/02216 , H01L21/0228 , H01L21/3141 , H01L21/3144 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/76224
摘要： A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no more than about a monolayer of material, capable of completely filling high aspect ratio trenches. Additionally, the trench-fill material composition can be tailored by processes described herein, particularly to match the coefficient of thermal expansion (CTE) to that of the surrounding substrate within which the trench is formed. Mixed phases of mullite and silica have been found to meet the goals of device isolation and matched CTE. The described process includes mixing atomic layer deposition cycles of aluminum oxide and silicon oxide in ratios selected to achieve the desired composition of the isolation material, namely on the order of 30% alumina and 70% silicon oxide by weight.
摘要翻译：通过原子层沉积形成电介质膜，以保形地填充狭窄的深沟槽，用于器件隔离。所示实施方案的方法包括交替地以一系列循环脉冲气相反应物，其中每个循环不超过约单层材料，能够完全填充高纵横比沟槽。此外，沟槽填充材料组合物可以通过本文所述的方法来定制，特别是使热膨胀系数（CTE）与其中形成沟槽的周围基底的热膨胀系数相匹配。已经发现莫来石和二氧化硅的混合相达到器件隔离和匹配CTE的目标。所描述的方法包括以选择的比例混合氧化铝和氧化硅的原子层沉积循环，以达到分离材料的所需组成，即按重量计30％氧化铝和70％氧化硅。

18. 发明授权

US06686271B2 Protective layers prior to alternating layer deposition 有权
标题翻译：交替层沉积之前的保护层
公开(公告)号：US06686271B2
公开(公告)日：2004-02-03
申请号：US10237526
申请日：2002-09-06
申请人： Ivo Raaijmakers , Pekka T. Soininen , Ernst H. A. Granneman , Suvi P. Haukka
发明人： Ivo Raaijmakers , Pekka T. Soininen , Ernst H. A. Granneman , Suvi P. Haukka
IPC分类号： H01L214763
CPC分类号： C23C16/045 , C23C16/45525 , H01L21/28562 , H01L21/32051 , H01L21/7681 , H01L21/76814 , H01L21/76825 , H01L21/76828 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L21/76856 , H01L21/76864 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.
摘要翻译：提供了用于集成电路中的双镶嵌结构的保形衬里的方法和结构，特别是在多孔材料中形成的开口。沟槽和接触通孔形成在绝缘层中。沟槽和通孔的侧壁上的孔堵塞，然后将结构暴露于交替的化学物质以形成所需衬里材料的单层。在示例性工艺流程中，密封层的化学或物理气相沉积（CVD或PVD）由于不完全的一致性而阻塞孔，并且之后是原子层沉积（ALD），特别是交替脉冲的金属卤化物和注入恒定的氨气载体流。交替的方法也可以布置成在绝缘体的孔内以CVD模式起作用，因为反应物不容易从脉冲之间的孔中吹扫。自身端接的金属层因此与氮气反应。接近完美的台阶覆盖允许扩散阻挡功能的最小厚度，从而使任何给定沟槽和通孔尺寸的后续填充金属的体积最大化。

19. 发明授权

US06482733B2 Protective layers prior to alternating layer deposition 有权
标题翻译：交替层沉积之前的保护层
公开(公告)号：US06482733B2
公开(公告)日：2002-11-19
申请号：US09843518
申请日：2001-04-26
申请人： Ivo Raaijmakers , Pekka T. Soininen , Ernst H. A. Granneman , Suvi P. Haukka
发明人： Ivo Raaijmakers , Pekka T. Soininen , Ernst H. A. Granneman , Suvi P. Haukka
IPC分类号： H01L214763
CPC分类号： C23C16/045 , C23C16/45525 , H01L21/28562 , H01L21/32051 , H01L21/7681 , H01L21/76814 , H01L21/76825 , H01L21/76828 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L21/76856 , H01L21/76864 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.
摘要翻译：提供了用于集成电路中的双镶嵌结构的保形衬里的方法和结构，特别是在多孔材料中形成的开口。沟槽和接触通孔形成在绝缘层中。沟槽和通孔的侧壁上的孔堵塞，然后将结构暴露于交替的化学物质以形成所需衬里材料的单层。在示例性工艺流程中，密封层的化学或物理气相沉积（CVD或PVD）由于不完全的一致性而阻塞孔，并且之后是原子层沉积（ALD），特别是交替脉冲的金属卤化物和注入恒定的氨气载体流。交替的方法也可以布置成在绝缘体的孔内以CVD模式起作用，因为反应物不容易从脉冲之间的孔中吹扫。自身端接的金属层因此与氮气反应。接近完美的台阶覆盖允许扩散阻挡功能的最小厚度，从而使任何给定沟槽和通孔尺寸的后续填充金属的体积最大化。

20. 发明授权

US07419903B2 Thin films 有权
标题翻译：薄膜
公开(公告)号：US07419903B2
公开(公告)日：2008-09-02
申请号：US11106220
申请日：2005-04-13
申请人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey
发明人： Suvi P. Haukka , Ivo Raaijmakers , Wei Min Li , Juhana Kostamo , Hessel Sprey
IPC分类号： H01L21/4763
CPC分类号： C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089
摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.
摘要翻译：通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。在所示实施例中，在循环过程中引入了不同量的杂质源。因此，即使对于非常薄的层也提供了渐变栅极电介质。薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。类似地，栅极电介质可以从氧化铝到氧化铝和较高介电材料（例如ZrO 2）的混合物变化为纯高k材料并返回到氧化铝。在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。在一些实施例中，提供了额外的种子层或附加的过渡层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式