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11. 发明申请

US20200134114A1 SUPERPOSITION OF CANONICAL TIMING VALUE REPRESENTATIONS IN STATISTICAL STATIC TIMING ANALYSIS 审中-公开
公开(公告)号：US20200134114A1
公开(公告)日：2020-04-30
申请号：US16169243
申请日：2018-10-24
申请人： International Business Machines Corporation
发明人： Eric Foreman , James Gregerson , Gregory Schaeffer , Michael H. Wood
IPC分类号： G06F17/50 , G06F17/18 , G06F17/16
摘要： A system and method to perform timing analysis in integrated circuit development involves defining an integrated circuit design as nodes representing components of the integrated circuit design that are interconnected by edges representing wires. Sequentially connected nodes define a path. Statistical variables are defined for a canonical delay model of each node and edge of the integrated circuit design and define a first set of conditions. The method includes performing a statistical static timing analysis to obtain an arrival time at each node as a sum of the canonical delay models for nodes and edges that precede the node in the path of the node, obtaining a projected arrival time at a second set of conditions for the node by scaling the arrival time for the node using scale factors that represent the second set of conditions and using a transformation matrix, and providing the integrated circuit design for fabrication.

12. 发明授权

US09928322B2 Simulation of modifications to microprocessor design 有权
公开(公告)号：US09928322B2
公开(公告)日：2018-03-27
申请号：US15135595
申请日：2016-04-22
申请人： International Business Machines Corporation
发明人： Christopher J. Berry , Chris A. Cavitt , Adam P. Matheny , Jose L. Neves , Jesse P. Surprise , Michael H. Wood
IPC分类号： G06F17/50 , G06F11/00
CPC分类号： G06F17/5031 , G06F11/00 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/68 , G06F2217/84
摘要： A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

13. 发明申请

US20170344693A1 PROGRAMMABLE CLOCK DIVISION METHODOLOGY WITH IN-CONTEXT FREQUENCY CHECKING 有权
公开(公告)号：US20170344693A1
公开(公告)日：2017-11-30
申请号：US15165058
申请日：2016-05-26
申请人： International Business Machines Corporation
发明人： Naiju K. Abdul , Jennifer E. Basile , Hemlata Gupta , Kerim Kalafala , Jeremy J. Leitzen , Stephen G. Shuma , Manish Verma , James D. Warnock , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/62 , G06F2217/84
摘要： A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for a timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.

14. 发明授权

US09646122B2 Variable accuracy parameter modeling in statistical timing 有权
公开(公告)号：US09646122B2
公开(公告)日：2017-05-09
申请号：US15235168
申请日：2016-08-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Alexander J. Suess , Chandramouli Visweswariah , Michael H. Wood
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031 , G06F17/5081 , G06F2217/84
摘要： Systems and methods compute a mean timing value of an integrated circuit design for variables using a first timing calculation of relatively higher accuracy; and calculate a first timing value of the integrated circuit design for the variables, using a second timing calculation having a relatively lower accuracy. Such systems and methods calculate second timing values of the integrated circuit design for additional sets of variables using the second timing calculation; and calculate finite differences of each of the second timing values to the first timing value. Thus, these systems and methods calculate a statistical sensitivity of the first timing value to the additional sets of variables based on the finite differences. Further, such systems and methods calculate a statistical sensitivity of the mean timing value to the additional sets of values based on the statistical sensitivity of the first timing value to the additional sets of values.

15. 发明授权

US09607124B2 Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints 有权
公开(公告)号：US09607124B2
公开(公告)日：2017-03-28
申请号：US14691599
申请日：2015-04-21
申请人： International Business Machines Corporation
发明人： Adil Bhanji , Kerim Kalafala , Ravichander Ledalla , Debjit Sinha , Chandramouli Visweswariah , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5036 , G06F2217/84
摘要： The timing analysis of an integrated chip component using dynamic load sensitive timing feedback constraints maintaining the timing accuracy for all the boundary paths is achieved by capturing a reduced order representation for parasitic load within a component for each of its primary input and primary output along with sensitivities of the arrival time, the slew and the required arrival time to the load representation at the component parent level of hierarchy as part of generating load sensitive feedback constraints. During the out-of-context timing closure of the component, the base load representation and the sensitivities, and an updated load representation enables the calculation of the updated boundary constraint for an accurate timing analysis. The accuracy improvement increases a chip designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing. The method is applicable for deterministic as well as for statistical timing analyses.

16. 发明授权

US09483604B1 Variable accuracy parameter modeling in statistical timing 有权
标题翻译：统计时序的可变精度参数建模
公开(公告)号：US09483604B1
公开(公告)日：2016-11-01
申请号：US14739279
申请日：2015-06-15
申请人： International Business Machines Corporation
发明人： Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Alexander J. Suess , Chandramouli Visweswariah , Michael H. Wood
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031 , G06F17/5081 , G06F2217/84
摘要： Systems and methods compute a mean timing value of an integrated circuit design for variables using a first timing calculation of relatively higher accuracy; and calculate a first timing value of the integrated circuit design for the variables, using a second timing calculation having a relatively lower accuracy. Such systems and methods calculate second timing values of the integrated circuit design for additional sets of variables using the second timing calculation; and calculate finite differences of each of the second timing values to the first timing value. Thus, these systems and methods calculate a statistical sensitivity of the first timing value to the additional sets of variables based on the finite differences. Further, such systems and methods calculate a statistical sensitivity of the mean timing value to the additional sets of values based on the statistical sensitivity of the first timing value to the additional sets of values.
摘要翻译：系统和方法使用相对较高精度的第一定时计算来计算变量的集成电路设计的平均定时值; 并且使用具有相对较低精度的第二定时计算来计算所述变量的集成电路设计的第一定时值。这样的系统和方法使用第二定时计算来计算用于附加变量集合的集成电路设计的第二定时值; 并计算每个第二定时值与第一定时值的有限差。因此，这些系统和方法基于有限差分来计算第一时间值对附加变量集合的统计灵敏度。此外，这样的系统和方法基于第一定时值对附加值集合的统计灵敏度来计算平均定时值对附加值集合的统计灵敏度。

17. 发明申请

US20160232273A1 METHOD FOR CALCULATING AN EFFECT ON TIMING OF MOVING A PIN FROM AN EDGE TO AN INBOARD POSITION IN PROCESSING LARGE BLOCK SYNTHESIS (LBS) 有权
标题翻译：用于计算处理大块合成（LBS）时将引脚从边缘移动到内部位置的时间的影响的方法
公开(公告)号：US20160232273A1
公开(公告)日：2016-08-11
申请号：US14619168
申请日：2015-02-11
申请人： International Business Machines Corporation
发明人： Lukas Daellenbach , Niels Fricke , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072
摘要： A computer-implemented method for calculating an effect on timing of moving a pin from an edge position to an inboard position in processing large block synthesis (LBS). The method includes determining first timing details at the inboard position, based on internal wire segments between a signal source and the inboard position. The method further includes selecting an upper metal layer as a virtual wire between the edge position and the inboard position. The method further includes calculating capacitance and resistance of the virtual wire. The method further includes updating driver strength of a driver between the signal source and the inboard position. The method further includes determining second timing details at the inboard position, based on wire loads of the virtual wire. The method further includes modifying an assertion of the pin at the inboard position, based on the first and the second timing details.
摘要翻译：一种计算机实现的方法，用于计算在处理大块合成（LBS）时将针从边缘位置移动到内侧位置的定时的影响。该方法包括基于信号源和内侧位置之间的内部线段来确定内侧位置处的第一定时细节。该方法还包括选择上金属层作为边缘位置和内侧位置之间的虚拟线。该方法还包括计算虚拟线的电容和电阻。该方法还包括更新驾驶员在信号源和内侧位置之间的驾驶员强度。该方法还包括基于虚拟线的有线负载来确定内侧位置处的第二定时细节。该方法还包括基于第一和第二定时细节来修改在内侧位置处的引脚的断言。

18. 发明申请

US20140108743A1 STORE DATA FORWARDING WITH NO MEMORY MODEL RESTRICTIONS 有权
标题翻译：存储数据转发，无内存模式限制
公开(公告)号：US20140108743A1
公开(公告)日：2014-04-17
申请号：US14059673
申请日：2013-10-22
申请人： International Business Machines Corporation
发明人： Brian D. Barrick , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Aaron Tsai , Chung-Lung K. Shum , Michael H. Wood
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F9/3826 , G06F9/3834
摘要： Embodiments relate to loading data in a pipelined microprocessor. An aspect includes issuing a load request that comprises a load address requiring at least one block of data the same size as a largest contiguous granularity of data returned from a cache. Another aspect includes determining that the load address matches at least one block address. Another aspect includes, based on determining that there is an address match, reading a data block from a buffer register and sending the data to satisfy the load request; comparing a unique set id of the data block to the set id of the matching address after sending the data block; based on determining that there is a set id match, continuing the load request, or, based on determining that there is not a set id match, setting a store-forwarding state of the matching address to no store-forwarding and rejecting the load request.
摘要翻译：实施例涉及在流水线微处理器中加载数据。一方面包括发布加载请求，该加载请求包括需要至少一个与高速缓存返回的最大连续粒度数据相同大小的数据块的加载地址。另一方面包括确定加载地址与至少一个块地址匹配。另一方面包括：基于确定存在地址匹配，从缓冲寄存器读取数据块并发送数据以满足加载请求; 在发送数据块之后，将数据块的唯一集合ID与匹配地址的集合ID进行比较; 基于确定存在设置id匹配，继续加载请求，或者基于确定没有设置id匹配，将匹配地址的存储转发状态设置为不存储转发并拒绝加载请求。

19. 发明申请

US20140096100A1 METHOD OF SHARING AND RE-USING TIMING MODELS IN A CHIP ACROSS MULTIPLE VOLTAGE DOMAINS 有权
标题翻译：在多个电压域中的芯片中共享和重新使用时序模型的方法
公开(公告)号：US20140096100A1
公开(公告)日：2014-04-03
申请号：US13633911
申请日：2012-10-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Debjit Sinha , Eric J. Fluhr , Stephen G. Shuma , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/84
摘要： A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts.
摘要翻译：考虑到制造和环境变化的VLSI电路或芯片设计的时序分析的方法和系统，其中设计包括通过共享和重新使用摘要在多于一个电压域上实例化的门或宏的多个实例。芯片的时序分析包括在抽象生成期间在不同于域的电压域中实例化的宏抽象。定时模型重新用于跨芯片电压域或芯片设计。此外，芯片设计的统计时序分析考虑了其中至少一个定时抽象模型生成时间电压域条件与芯片中的宏实例化域不同的电压域。本发明还提供共享和重新使用统计时序模型或摘要。

20. 发明申请

US20180330032A1 INDEPENDENTLY PROJECTING A CANONICAL CLOCK 审中-公开
公开(公告)号：US20180330032A1
公开(公告)日：2018-11-15
申请号：US15592351
申请日：2017-05-11
申请人： International Business Machines Corporation
发明人： Nathan Buck , Sean M. Carey , Peter C. Elmendorf , Eric A. Foreman , Jeffrey G. Hemmett , Lyle Jackson , Kerim Kalafala , Stephen G. Shuma , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F17/5045 , G06F17/505 , G06F2217/10 , G06F2217/12
摘要： A design and timing model for at least one circuit path of at least a portion of an IC design is loaded into a computer. At least one canonical clock variable associated with the model is defined; it includes at least one source of variation. The computer is used to perform an SSTA of the at least one circuit path, based on the design and timing model and the at least one canonical clock variable, to obtain slack canonical data. A clock period is projected, based on the slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical. Results of the SSTA and the projected clock period are output to determine performance compliance. Efficient operation of the computer is enhanced by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation.

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