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1. 发明授权

US09910952B2 Hierarchically aware interior pinning for large synthesis blocks 有权
公开(公告)号：US09910952B2
公开(公告)日：2018-03-06
申请号：US15198954
申请日：2016-06-30
申请人： International Business Machines Corporation
发明人： Matthew D. Affeldt , Christopher J. Berry , Randall J. Darden , Shyam Ramji , Eddy St. Juste
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.

2. 发明申请

US20180060447A1 SCOPING SEARCHES WITHIN WEBSITES 审中-公开
公开(公告)号：US20180060447A1
公开(公告)日：2018-03-01
申请号：US15788965
申请日：2017-10-20
申请人： International Business Machines Corporation
发明人： Christopher J. Berry , Mark C. Hampton
IPC分类号： G06F17/30
CPC分类号： G06F16/957
摘要： A computer-implemented method, computer program product, and computing system is provided for scoping searches within a website. In an implementation, a method may receiving a search request. The method may also include identifying a location of a search scoping feature within a website hierarchy. The method may further include setting a search scope relative to the search request based on, at least in part, the location of the search scoping feature.

3. 发明授权

US09715565B2 Physical aware technology mapping in synthesis 有权
公开(公告)号：US09715565B2
公开(公告)日：2017-07-25
申请号：US15169924
申请日：2016-06-01
申请人： International Business Machines Corporation
发明人： Christopher J. Berry , Pinaki Chakrabarti , Lakshmi N. Reddy , Sourav Saha
IPC分类号： G06F17/00 , G06F17/50
CPC分类号： G06F17/505 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/84
摘要： A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The system includes a memory device to store a logic design of the integrated circuit, and a processor to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each latch in a logic design based on an algorithm, to determine a location of each combinational logic gate in the logic design, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays.

4. 发明申请

US20170046464A1 SLACK REDISTRIBUTION FOR ADDITIONAL POWER RECOVERY 有权
标题翻译：用于附加功率恢复的滑块重新分配
公开(公告)号：US20170046464A1
公开(公告)日：2017-02-16
申请号：US14879216
申请日：2015-10-09
申请人： International Business Machines Corporation
发明人： Christopher J. Berry , Yiu-Hing Chan , Arjen A. Mets , Charudhattan Nagarajan , Ricardo H. Nigaglioni , Sourav Saha , Hameedbasha Shaik
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045 , G06F17/5054 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/78 , G06F2217/84
摘要： A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.
摘要翻译：描述了实现集成电路设计的系统和方法。该方法包括基于由多个周期边界定义的多个周期的当前小区选择，布置和路由获得当前定时松弛值的定时数据库，每个周期表示相应的多个周期边界对之间的设备，识别用于松弛再分配的多个周期边界之间的候选周期边界，候选周期边界中的每一个与正时序松弛相关联，并且选择候选周期边界之间的再分配周期边界。基于再分配与再分配周期边界相关联的正定时松弛来生成修改的定时数据库，并且使用修改的定时数据库执行功率恢复，以减少再分配周期边界中的一个以上的功率。

5. 发明授权

US09552451B1 Cross-hierarchy interconnect adjustment for power recovery 有权
标题翻译：电源恢复的跨层级互连调整
公开(公告)号：US09552451B1
公开(公告)日：2017-01-24
申请号：US15055031
申请日：2016-02-26
申请人： International Business Machines Corporation
发明人： Christopher J. Berry , Ricardo H. Nigaglioni , Haifeng Qian , Sourav Saha
IPC分类号： G06F17/00 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/06 , G06F2217/84
摘要： Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.
摘要翻译：实施例涉及跨层次互连调整。一个方面包括接收对应于芯片设计的芯片布局数据，其中将芯片设计的金属堆叠的第一部分分配给第一层次，并且金属堆叠的第二部分基于第第一和第二层次。另一方面包括确定金属堆叠的第一部分的未使用部分。另一方面包括将第二层次的互连从分配给第二层的金属堆叠的第二部分移动到芯片布局数据中的金属堆叠的第一部分的未使用部分。另一方面包括基于通过互连的移动在芯片设计中产生的松弛余量的量来移动互连之后在芯片布局数据上执行功率恢复。

6. 发明申请

US20170011163A1 HIERARCHICAL WIRE-PIN CO-OPTIMIZATION 有权
公开(公告)号：US20170011163A1
公开(公告)日：2017-01-12
申请号：US14879186
申请日：2015-10-09
申请人： International Business Machines Corporation
发明人： Christopher J. Berry , Ajith Kumar M. Chandrasekaran , Randall J. Darden , Shyam Ramji , Sourav Saha
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F17/5077 , G06F2217/84
摘要： A method and system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization are described. The method includes providing boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the boundary conditions including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros, performing macro-level physical synthesis at each of the plurality of macros, and providing feedback to the unit level controller based on the macro-level physical synthesis performed at each of the plurality of macros, the feedback including a proposed new location for the movable pins of each of the plurality of blocks. The method also includes performing hierarchical co-optimization at the unit level controller based on the feedback from each of the plurality of macros to determine locations for the movable pins.

7. 发明申请

US20160217248A1 CRITICAL REGION IDENTIFICATION 审中-公开
标题翻译：关键区域识别
公开(公告)号：US20160217248A1
公开(公告)日：2016-07-28
申请号：US15090982
申请日：2016-04-05
申请人： International Business Machines Corporation
发明人： George Antony , Christopher J. Berry , Ricardo H. Nigaglioni , Sridhar H. Rangarajan , Sourav Saha , Vinay K. Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/50 , G06F17/5022 , G06F17/5045 , G06F17/505 , G06F17/5072 , G06F17/5077 , G06F2217/78
摘要： A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.
摘要翻译：描述了用于识别用于重新设计的集成电路的设计块的区域的方法和系统。该方法包括将设计块划分为网格，每个网格包括相应数量的逻辑元素。该方法还包括基于指定的标准来过滤每个网格，该过滤包括确定满足指定标准的每个网格中的逻辑元素的总数（A）中的相应逻辑元素的数目（B）。该区域是基于过滤结果的两个或更多个网格的集合。

8. 发明授权

US09378326B2 Critical region identification 有权
标题翻译：关键区域识别
公开(公告)号：US09378326B2
公开(公告)日：2016-06-28
申请号：US14481154
申请日：2014-09-09
申请人： International Business Machines Corporation
发明人： George Antony , Christopher J. Berry , Ricardo H. Nigaglioni , Sridhar H. Rangarajan , Sourav Saha , Vinay K. Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/50 , G06F17/5022 , G06F17/5045 , G06F17/505 , G06F17/5072 , G06F17/5077 , G06F2217/78
摘要： A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.
摘要翻译：描述了用于识别用于重新设计的集成电路的设计块的区域的方法和系统。该方法包括将设计块划分为网格，每个网格包括相应数量的逻辑元素。该方法还包括基于指定的标准来过滤每个网格，该过滤包括确定满足指定标准的每个网格中的逻辑元素的总数（A）中的相应逻辑元素的数目（B）。该区域是基于过滤结果的两个或更多个网格的集合。

9. 发明授权

US10229238B2 Congestion aware layer promotion 有权
公开(公告)号：US10229238B2
公开(公告)日：2019-03-12
申请号：US15338630
申请日：2016-10-31
申请人： International Business Machines Corporation
发明人： Christopher J. Berry , Lakshmi Reddy , Sourav Saha
IPC分类号： G06F17/50
摘要： Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes a system to manage layer promotion in a routing phase of integrated circuit design. The system includes a memory device to store instructions, and a processor to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects.

10. 发明授权

US10157255B2 Hierarchically aware interior pinning for large synthesis blocks 有权
公开(公告)号：US10157255B2
公开(公告)日：2018-12-18
申请号：US15823705
申请日：2017-11-28
申请人： International Business Machines Corporation
发明人： Matthew D. Affeldt , Christopher J. Berry , Randall J. Darden , Shyam Ramji , Eddy St. Juste
IPC分类号： G06F17/50
摘要： A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.

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