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11. 发明授权

US09698089B2 Substrate device and electric circuit arrangement having first substrate section perpendicular to second substrate section 有权
公开(公告)号：US09698089B2
公开(公告)日：2017-07-04
申请号：US15191729
申请日：2016-06-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Brunschwiler , Dominic Gschwend , Keiji Matsumoto , Stefano S. Oggioni , Gerd Schlottig , Timo J. Tick , Jonas Zuercher
IPC分类号： H01L21/76 , H01L23/498 , H05K1/02 , H01L23/14 , H01L23/373 , H01L23/367 , H05K3/34 , H05K3/40
CPC分类号： H01L23/49822 , H01L23/14 , H01L23/367 , H01L23/3735 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L2224/16225 , H01L2224/73253 , H01L2924/0002 , H05K1/0206 , H05K1/0298 , H05K3/3436 , H05K3/4046 , H05K2201/048 , Y10T29/49126 , H01L2924/00
摘要： An electronic circuit includes a substrate device which includes a first substrate section including a first plurality of layers attached to each other having a first orientation (x2) and a second substrate section including a second plurality of layers attached to each other. The second plurality of layers have a second orientation (x3). The first orientation (x2) and the second orientation (x3) are perpendicular with respect to one another.

12. 发明申请

US20150248516A1 REDUCTION OF WARPAGE OF MULTILAYERED SUBSTRATE OR PACKAGE 有权
标题翻译：减少多层基板或包装的保修
公开(公告)号：US20150248516A1
公开(公告)日：2015-09-03
申请号：US14193004
申请日：2014-02-28
申请人： International Business Machines Corporation
发明人： Sayuri Hada , Keiji Matsumoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5018 , G06F17/5068 , G06F17/5077 , G06F17/5086 , G06F2217/12 , Y02P90/265
摘要： A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, Δα, varies in a substrate. The method focuses in on the difference in Δα with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in Δα with a smaller length scale (high frequency) and corrects only the difference in Δα with a greater length scale. The distribution of the difference in Δα in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in Δα with a low frequency and the difference in Δα between before and after correction, thereby revealing a part that requires correction.
摘要翻译：一种减少布线层的调整以减少多层基板的翘曲的方法，并且能够定位需要校正的布线层的一部分以减少翘曲。平均热膨胀系数ΔDgα的差在基板中变化。该方法的重点在于具有较大长度尺度（低频）的差异，与具有较小长度尺度（高频率）的差异具有比较显着的翘曲效应，并且仅纠正差异 in＆Dgr;α具有更大的长度尺度。确定底物平面上的＆Dgr;α差异的分布。然后进行数字滤波，仅提取低频的Dgr;α和校正前后的Dgr;α的差异，从而显示需要校正的部分。

13. 发明公开

US20240334616A1 HEAT SPREADER FOR MODIFIED EDGE COOLING 审中-公开
公开(公告)号：US20240334616A1
公开(公告)日：2024-10-03
申请号：US18194597
申请日：2023-03-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Keiji Matsumoto , Mukta Ghate Farooq , John Knickerbocker
IPC分类号： H05K3/46 , H05K1/02 , H05K1/11 , H05K3/00 , H05K7/20
CPC分类号： H05K3/4602 , H05K1/0212 , H05K1/0218 , H05K1/024 , H05K1/115 , H05K3/0017 , H05K3/0055 , H05K7/20509 , H05K2201/09145
摘要： A method for manufacturing an electronic package includes etching one or more lateral surfaces of a PCB laminate to expose power and ground planes of the PCB laminate. A protective coating is applied to the exposed power and ground planes. At least one heat-generating component is affixed to a top surface of the PCB laminate. A heat spreader having a base section and flanged edges is formed and attached to the heat-generating components and the PCB laminate lateral surfaces, where the flanged edges of the heat spreader are thermally connected to the PCB laminate lateral surfaces. During operation of the heat-generating components, the flanged edges dissipate heat from the PCB laminate lateral surfaces.

14. 发明公开

US20240120705A1 ISOLATING HEAT SPREADER 审中-公开
公开(公告)号：US20240120705A1
公开(公告)日：2024-04-11
申请号：US17962434
申请日：2022-10-07
申请人： International Business Machines Corporation
发明人： Keiji Matsumoto , Mukta Ghate Farooq , John Knickerbocker
IPC分类号： H01S5/024 , H01L23/367 , H01L23/373
CPC分类号： H01S5/02469 , H01L23/367 , H01L23/373
摘要： A heat spreader apparatus includes a first portion; a second portion; and a connecting portion between the first and second portions, with high-conductivity axes and a low-conductivity axis, the low-conductivity axis being directed between the first and second portions. In one or more embodiments, the first, second, and connecting portions are thermally anisotropic blocks, and the apparatus forms a rectangular prism.

15. 发明公开

US20240006371A1 SEMICONDUCTOR DEVICE INTERCONNECT STRUCTURE 审中-公开
公开(公告)号：US20240006371A1
公开(公告)日：2024-01-04
申请号：US17809574
申请日：2022-06-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Keiji Matsumoto , Toyohiro Aoki , Takahito Watanabe , RISA MIYAZAWA , Takashi Hisada
IPC分类号： H01L23/00
CPC分类号： H01L24/81 , H01L24/11 , H01L24/16 , H01L24/29 , H01L2224/11849 , H01L2224/1148 , H01L2224/16237 , H01L2224/2902 , H01L2224/0401 , H01L2224/73204 , H01L2224/81815
摘要： An interconnect system may connect a first semiconductor device with second semiconductor device. The interconnect system includes patterned mask, conductive pads, solder bumps, and an adhesion layer. The patterned mask may be retained after it is utilized to fabricate the conductive pads and the solder bumps. The patterned mask may be thinned, and the adhesion layer may be formed upon the thinned patterned mask and upon the solder bumps. The adhesion layer and the solder bumps may be partially removed or planarized and the top surface of the adhesion layer that remains between the solder bumps may be coplanar with the top surface of the solder bumps.

16. 发明授权

US11647954B2 Ear device for heat stroke detection 有权
公开(公告)号：US11647954B2
公开(公告)日：2023-05-16
申请号：US16677881
申请日：2019-11-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Keiji Matsumoto , Bruno Michel
IPC分类号： A61B5/00 , A61B5/01 , A61B5/087 , A61B5/024
CPC分类号： A61B5/6817 , A61B5/0008 , A61B5/01 , A61B5/02433 , A61B5/0878 , A61B5/4266
摘要： A method is presented for predicting heat stroke of a subject. The method includes an earbud covered with a waterproof moisture permeable membrane allowing for moisture penetration, the earbud including an infrared (IR) temperature sensor for measuring core body temperature of the subject, wherein the IR temperature sensor is covered with a waterproof IR transmittable film to inhibit water drops from contacting a detector of the IR temperature sensor, a first humidity sensor positioned within a sweat flow path within the earbud, a second humidity sensor positioned outside the earbud, and a sodium ion (Na+) concentration sensor for measuring hydration levels of the subject.

17. 发明授权

US10637105B2 Battery embedded architecture for supplying appropriate voltage 有权
公开(公告)号：US10637105B2
公开(公告)日：2020-04-28
申请号：US15697848
申请日：2017-09-07
申请人： International Business Machines Corporation
发明人： Keiji Matsumoto , Hiroyuki Mori
IPC分类号： H01M10/42 , H01M2/10 , H01M10/48 , H01M10/0585 , H01M2/02 , H01M2/26 , H01M10/04 , H05K1/11 , H05K1/18 , H05K3/46 , H01M10/0562 , H01M2/30 , H05K1/02 , H01M10/052 , H01M10/0525
CPC分类号： H01M10/425 , H01M2/0202 , H01M2/1022 , H01M2/26 , H01M2/30 , H01M10/044 , H01M10/049 , H01M10/0445 , H01M10/0562 , H01M10/0585 , H01M10/482 , H05K1/0262 , H05K1/111 , H05K1/115 , H05K1/185 , H01M10/052 , H01M10/0525 , H01M2220/30 , H01M2300/0068 , H05K3/4602 , H05K2201/10037 , H05K2201/10106 , H05K2203/1469
摘要： A battery embedded structure is disclosed. The battery embedded structure comprises a substrate including one or more stacked battery units. Each stacked battery unit includes two or more conductive layers and one or more unit cells. Each unit cell is disposed between two conductive layers. The substrate has a principal surface provided by one or more respective side surfaces of the one or more stacked battery units. The battery embedded structure also comprises a wiring layer disposed on the principal surface of the substrate. The wiring layer includes a plurality of electrical paths and a plurality of vias. Each via is connected with one electrical path. Each via is located at a position corresponding to an edge surface of a conductive layer of the two or more conductive layers of the one or more stacked battery units so as to contact electrically to that conductive layer.

18. 发明授权

US09941230B2 Electrical connecting structure between a substrate and a semiconductor chip 有权
公开(公告)号：US09941230B2
公开(公告)日：2018-04-10
申请号：US14985009
申请日：2015-12-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Keiji Matsumoto , Keishi Okamoto , Yasumitsu K. Orii , Kazushige Toriyama
IPC分类号： H01L23/00 , G02B6/42
CPC分类号： H01L24/13 , G02B6/4219 , G02B6/4232 , G02B6/4274 , H01L24/16 , H01L24/81 , H01L2224/11312 , H01L2224/1146 , H01L2224/1147 , H01L2224/13023 , H01L2224/13082 , H01L2224/131 , H01L2224/13124 , H01L2224/13147 , H01L2224/13166 , H01L2224/1319 , H01L2224/1601 , H01L2224/16058 , H01L2224/16237 , H01L2224/81191 , H01L2224/814 , H01L2224/81815 , H01L2225/06513 , H01L2924/014 , H01L2924/351 , H01L2924/3841 , H01L2924/00014 , H01L2924/0665
摘要： The present invention provides an electrical connecting structure between a substrate 21 and a semiconductor chip 22. The electrical connecting structure comprises a metal bump 26 formed on a contact pad 28 of a semiconductor chip 22 and a coating layer 25 formed on the metal bump 26 of the semiconductor chip 22. The coating layer includes material not wettable with solder. The electrical connecting structure further comprises a metal pad 24 formed on the substrate 21. The electrical connecting structure further comprises a solder 29 connecting to a side surface of the metal bump 26 and an outer surface of the metal pad 24. The outer surface is not covered by the coating layer 25.

19. 发明授权

US09384314B2 Reduction of warpage of multilayered substrate or package 有权
标题翻译：降低多层基材或包装的翘曲
公开(公告)号：US09384314B2
公开(公告)日：2016-07-05
申请号：US14193004
申请日：2014-02-28
申请人： International Business Machines Corporation
发明人： Sayuri Hada , Keiji Matsumoto
IPC分类号： H01L21/20 , G06F17/50
CPC分类号： G06F17/5081 , G06F17/5018 , G06F17/5068 , G06F17/5077 , G06F17/5086 , G06F2217/12 , Y02P90/265
摘要： A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, Δα, varies in a substrate. The method focuses in on the difference in Δα with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in Δα with a smaller length scale (high frequency) and corrects only the difference in Δα with a greater length scale. The distribution of the difference in Δα in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in Δα with a low frequency and the difference in Δα between before and after correction, thereby revealing a part that requires correction.
摘要翻译：一种减少布线层的调整以减少多层基板的翘曲的方法，并且能够定位需要校正的布线层的一部分以减少翘曲。平均热膨胀系数ΔDgα的差在基板中变化。该方法的重点在于具有较大长度尺度（低频）的差异，与具有较小长度尺度（高频率）的差异具有比较显着的翘曲效应，并且仅纠正差异 in＆Dgr;α具有更大的长度尺度。确定底物平面上的＆Dgr;α差异的分布。然后进行数字滤波，仅提取低频的Dgr;α和校正前后的Dgr;α的差异，从而显示需要校正的部分。

20. 发明申请

US20150278417A1 ACHIEVING POWER SUPPLY AND HEAT DISSIPATION (COOLING) IN THREE-DIMENSIONAL MULTILAYER PACKAGE 审中-公开
标题翻译：在三维多层包装中实现电源和散热（冷却）
公开(公告)号：US20150278417A1
公开(公告)日：2015-10-01
申请号：US14740906
申请日：2015-06-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Keiji Matsumoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5009 , G06F17/5068 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/15311 , H05K3/10 , H05K7/205 , Y10T29/49162
摘要： A computer-implemented structure for optimizing a route for power supply and heat dissipation in a multilayer chip. The method includes: setting a heat conductive thermal value for the multilayer chip by way of density, preparing a substrate that contains silicon where a wiring layer is formed facing the upper surface side of the multilayer chip, setting the power from the wiring layer of the substrate that uses silicon, manipulating the value of the power supply, and manipulating the heat conductive thermal value based on density. Both apparatus's include an organic substrate, a multilayer chip, a substrate containing silicon, a wiring layer, and a heat dissipater, wherein the components are configured to perform the steps of the above method. The method of configuring an apparatus ensures that all the multilayer chips are stored in the concave part of the organic substrate.
摘要翻译：一种用于优化多层芯片中的供电和散热路线的计算机实现的结构。该方法包括：通过密度设定多层芯片的导热热值，制备含有硅的基板，其中形成面对多层芯片的上表面侧的布线层，设置来自多层芯片的布线层的电力使用硅的衬底，操纵电源的值，以及基于密度来操纵导热热值。这两种装置包括有机基板，多层芯片，含硅的基板，布线层和散热器，其中所述部件被配置为执行上述方法的步骤。配置装置的方法确保所有多层芯片都存储在有机基板的凹部中。

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