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11. 发明授权

US06605996B2 Automatically gain controllable linear differential amplifier using variable degeneration resistor 有权
标题翻译：使用可变退化电阻自动增益可控线性差分放大器
公开(公告)号：US06605996B2
公开(公告)日：2003-08-12
申请号：US10039542
申请日：2001-12-31
申请人： Hyun Kyu Yu , Sang-Gug Lee , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Seon-Ho Han , Nam-Soo Kim
发明人： Hyun Kyu Yu , Sang-Gug Lee , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Seon-Ho Han , Nam-Soo Kim
IPC分类号： H03F345
CPC分类号： H03G1/007 , H03F3/45179 , H03F2203/45492 , H03G1/0023
摘要： An automatically gain controllable linear differential amplifier using a variable degeneration resistor is disclosed. The linear differential amplifier includes an input end, a bias current source, a load unit, a first MOS transistor and a second MOS transistor. The linear differential amplifiers of the present invention can control an amplifying gain according to an input signal and improve linearity IIP3 without needing additional power consumption caused by improving the linearity. The automatically gain controllable linear differential amplifier uses NMOS/PMOS transistor so an integration process of the amplifier can be implemented more conveniently and efficiently.
摘要翻译：公开了一种使用可变退化电阻的自动增益可控线性差分放大器。线性差分放大器包括输入端，偏置电流源，负载单元，第一MOS晶体管和第二MOS晶体管。本发明的线性差分放大器可以根据输入信号控制放大增益，并提高线性度IIP3，而不需要通过提高线性度而引起的附加功耗。自动增益可控线性差分放大器使用NMOS / PMOS晶体管，因此可以更方便，高效地实现放大器的集成过程。

12. 发明授权

US09294135B2 Digital radio frequency (RF) receiver 有权
标题翻译：数字射频（RF）接收机
公开(公告)号：US09294135B2
公开(公告)日：2016-03-22
申请号：US13609638
申请日：2012-09-11
申请人： Ik Soo Eo , Sang-Kyun Kim , Mun Yang Park , Seon-Ho Han , Hyun Kyu Yu
发明人： Ik Soo Eo , Sang-Kyun Kim , Mun Yang Park , Seon-Ho Han , Hyun Kyu Yu
IPC分类号： H04B1/00
CPC分类号： H04B1/0021
摘要： A digital RF receiver does not use a separate receiver according to a mode and a band for multi-mode reception, MIMO reception, and bandwidth extension reception, and changes only setting variables in a single receiver structure so as to implement multi-mode reception, MIMO reception, bandwidth extension reception, and/or simultaneous multi-mode operation, such that complexity of the receiver, development cost, and power consumption can be reduced.
摘要翻译：数字RF接收机根据用于多模式接收，MIMO接收和带宽扩展接收的模式和频带不使用单独的接收机，并且仅改变单个接收机结构中的设置变量以便实现多模式接收， MIMO接收，带宽扩展接收和/或同时多模式操作，从而可以减少接收机的复杂性，开发成本和功耗。

13. 发明授权

US09276800B2 Single frequency synthesizer based FDD transceiver 有权
标题翻译：基于单频合成器的FDD收发器
公开(公告)号：US09276800B2
公开(公告)日：2016-03-01
申请号：US13608677
申请日：2012-09-10
申请人： Hyun Ho Boo , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
发明人： Hyun Ho Boo , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
IPC分类号： H04J1/02 , H04L27/38 , H04L27/20 , H04L27/233 , H04L27/36 , H04B1/00
CPC分类号： H04L27/3836 , H04B1/0007 , H04L27/206 , H04L27/2092 , H04L27/2332 , H04L27/362 , H04L27/3854
摘要： The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.
摘要翻译：本发明涉及一种基于单频合成器的FDD收发器。单个频率合成器产生并提供载波频率，使得可以在发送和接收时执行上变频和下变频。因此，可以降低整个系统的面积，功耗和设计复杂性，并且可以提高系统的性能。

14. 发明授权

US06668035B2 Structure of delta-sigma fractional type divider 有权
$Structure of delta-sigma fractional type divider$
标题翻译： delta-sigma分数分频器的结构
公开(公告)号：US06668035B2
公开(公告)日：2003-12-23
申请号：US10179840
申请日：2002-06-24
申请人： Seon Ho Han , Jang Hong Choi , Jae Hong Jang , Hyun Kyu Yu
发明人： Seon Ho Han , Jang Hong Choi , Jae Hong Jang , Hyun Kyu Yu
IPC分类号： H03K2100
CPC分类号： H03M7/3022 , H03L7/1978
摘要： The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.
摘要翻译：本发明涉及一种delta-sigma分数型分频器的结构。分频器结构增加了Δ-Σ调制器的外部输入值和输出值，以调制吞咽计数器的值。因此，本发明可以提供一种Δ-Σ分数分频器，其结构简单，并且可以获得具有宽带频率混合能力的Δ-Σ模式的结构的效果。

15. 发明申请

US20130156141A1 DIGITAL RADIO FREQUENCY (RF) RECEIVER 有权
标题翻译：数字无线电频率（RF）接收机
公开(公告)号：US20130156141A1
公开(公告)日：2013-06-20
申请号：US13609638
申请日：2012-09-11
申请人： Ik Soo Eo , Sang-Kyun Kim , Mun Yang Park , Seon-Ho Han , Hyun Kyu Yu
发明人： Ik Soo Eo , Sang-Kyun Kim , Mun Yang Park , Seon-Ho Han , Hyun Kyu Yu
IPC分类号： H04B1/10
CPC分类号： H04B1/0021
摘要： A digital RF receiver does not use a separate receiver according to a mode and a band for multi-mode reception, MIMO reception, and bandwidth extension reception, and changes only setting variables in a single receiver structure so as to implement multi-mode reception, MIMO reception, bandwidth extension reception, and/or simultaneous multi-mode operation, such that complexity of the receiver, development cost, and power consumption can be reduced.
摘要翻译：数字RF接收机根据用于多模式接收，MIMO接收和带宽扩展接收的模式和频带不使用单独的接收机，并且仅改变单个接收机结构中的设置变量以便实现多模式接收， MIMO接收，带宽扩展接收和/或同时多模式操作，从而可以减少接收机的复杂性，开发成本和功耗。

16. 发明申请

US20110148490A1 TIME-TO-DIGITAL CONVERTER AND ALL DIGITAL PHASE-LOCKED LOOP INCLUDING THE SAME 有权
标题翻译：时数转换器和所有数字相位锁定环路
公开(公告)号：US20110148490A1
公开(公告)日：2011-06-23
申请号：US12956498
申请日：2010-11-30
申请人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
IPC分类号： H03L7/08 , H03M1/50
CPC分类号： H03L7/095 , G04F10/005 , H03L7/085 , H03L7/103 , H03L2207/50
摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.
摘要翻译：全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出来改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

17. 发明申请

US20100322361A1 DIGITAL RECEIVER 有权
标题翻译：数字接收机
公开(公告)号：US20100322361A1
公开(公告)日：2010-12-23
申请号：US12818510
申请日：2010-06-18
申请人： Seon-Ho HAN , Hyun Kyu Yu
发明人： Seon-Ho HAN , Hyun Kyu Yu
IPC分类号： H04L27/08
CPC分类号： H04B1/0025 , H04B1/001
摘要： In a digital receiver, a noise attenuation and signal magnitude mapping variable amplifying unit includes a filter and an amplifier, amplifies and band-bass filters an analog signal and attenuating white noise and an interference signal other than a band signal. An ADC performs sub sampling on a carrier frequency of a desired signal and performs oversampling on the band of the desired signal by using a sampling frequency to convert the analog signal which has passed through the noise attenuation and signal magnitude mapping variable amplifying unit into a digital signal of a direct conversion frequency band or an intermediate frequency band. The ADC has a dynamic range for processing both the desired signal and an undesired signal adjacent to the desired signal. A digital signal processing unit converts a signal frequency of the digital signal or digital-filters an undesired signal within the digital signal and processes the digital signal by digitally adjusting a gain.
摘要翻译：在数字接收机中，噪声衰减和信号幅度映射可变放大单元包括滤波器和放大器，对模拟信号进行放大和频带滤波，并衰减白噪声和除频带信号之外的干扰信号。 ADC对期望信号的载波频率进行子采样，并通过使用采样频率对已经通过噪声衰减和信号幅度可变放大单元的模拟信号进行数字化处理，对期望信号的频带进行过采样，直接转换频带或中频带的信号。 ADC具有用于处理期望信号和与期望信号相邻的不期望信号的动态范围。数字信号处理单元转换数字信号的信号频率或数字滤波数字信号内的不需要的信号，并通过数字调节增益来处理数字信号。

18. 发明授权

US07348849B2 Variable gain amplifier 有权
标题翻译：可变增益放大器
公开(公告)号：US07348849B2
公开(公告)日：2008-03-25
申请号：US11497461
申请日：2006-08-01
申请人： Seon Ho Han , Hyun Kyu Yu
发明人： Seon Ho Han , Hyun Kyu Yu
IPC分类号： H03F3/45 , H03G3/10
CPC分类号： H03G1/007 , H03F1/342 , H03F3/211 , H03F3/45206 , H03F3/45659 , H03F2200/15 , H03F2203/21154 , H03F2203/45008 , H03F2203/45302 , H03G7/06
摘要： A complementary metal oxide semiconductor (CMOS) variable gain amplifier has a wider decibel-linear gain variation characteristic with respect to a control voltage when a signal is amplified. The variable gain amplifier includes: a bias input circuit for supplying a current corresponding to a bias voltage; an operation region combination and feedback circuit connected to the bias input circuit and combining at least two amplifiers by feedback in response to a control voltage, each amplifier having a decibel-linear characteristic in saturation and triode regions of a complementary metal oxide semiconductor (CMOS); and a bias output circuit connected to the bias input circuit, and outputting bias current controlled by the operation region combination and feedback circuit.
摘要翻译：互补金属氧化物半导体（CMOS）可变增益放大器在信号被放大时相对于控制电压具有更宽的分贝线性增益变化特性。可变增益放大器包括：偏置输入电路，用于提供对应于偏置电压的电流; 连接到偏置输入电路的操作区域组合和反馈电路，并且通过响应于控制电压的反馈来组合至少两个放大器，每个放大器在互补金属氧化物半导体（CMOS）的饱和度和三极管区域中具有分贝线性特性， ; 以及偏置输出电路，连接到偏置输入电路，并输出由操作区域组合和反馈电路控制的偏置电流。

19. 发明申请

US20070132513A1 Variable gain amplifier 有权
标题翻译：可变增益放大器
公开(公告)号：US20070132513A1
公开(公告)日：2007-06-14
申请号：US11497461
申请日：2006-08-01
申请人： Seon Ho Han , Hyun Kyu Yu
发明人： Seon Ho Han , Hyun Kyu Yu
IPC分类号： H03G3/10
CPC分类号： H03G1/007 , H03F1/342 , H03F3/211 , H03F3/45206 , H03F3/45659 , H03F2200/15 , H03F2203/21154 , H03F2203/45008 , H03F2203/45302 , H03G7/06
摘要： A complementary metal oxide semiconductor (CMOS) variable gain amplifier has a wider decibel-linear gain variation characteristic with respect to a control voltage when a signal is amplified. The variable gain amplifier includes: a bias input circuit for supplying a current corresponding to a bias voltage; an operation region combination and feedback circuit connected to the bias input circuit and combining at least two amplifiers by feedback in response to a control voltage, each amplifier having a decibel-linear characteristic in saturation and triode regions of a complementary metal oxide semiconductor (CMOS); and a bias output circuit connected to the bias input circuit, and outputting bias current controlled by the operation region combination and feedback circuit.
摘要翻译：互补金属氧化物半导体（CMOS）可变增益放大器在信号被放大时相对于控制电压具有更宽的分贝线性增益变化特性。可变增益放大器包括：偏置输入电路，用于提供对应于偏置电压的电流; 连接到偏置输入电路的操作区域组合和反馈电路，并且通过响应于控制电压的反馈来组合至少两个放大器，每个放大器在互补金属氧化物半导体（CMOS）的饱和度和三极管区域中具有分贝线性特性， ; 以及偏置输出电路，连接到偏置输入电路，并输出由操作区域组合和反馈电路控制的偏置电流。

20. 发明授权

US09013347B2 Radar apparatus 有权
标题翻译：雷达装置
公开(公告)号：US09013347B2
公开(公告)日：2015-04-21
申请号：US13445102
申请日：2012-04-12
申请人： Pil Jae Park , Cheon Soo Kim , Hyun Kyu Yu , Min Park , Ik Soo Eo
发明人： Pil Jae Park , Cheon Soo Kim , Hyun Kyu Yu , Min Park , Ik Soo Eo
IPC分类号： G01S13/74 , G01S13/08 , G01S13/58 , G01S13/32 , G01S7/00
CPC分类号： G01S13/325 , G01S7/003 , G01S13/584
摘要： An embodiment of the present invention relates to a radar apparatus, wherein a distance to a target and a velocity of the target are measured by transmitting a digitally modulated transmitting signal using a digital code and receiving and demodulating an echo signal returned due to reflection of the transmitting signal from the target.
摘要翻译：本发明的实施例涉及一种雷达装置，其中通过使用数字码发送数字调制的发射信号来测量与目标的距离和目标的速度，并且接收和解调由于反射而返回的回波信号从目标传输信号。

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